Ahuja / Lakshminarayana / Shukla Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
1. Auflage 2011
ISBN: 978-1-4614-0872-7
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark
E-Book, Englisch, 170 Seiten, eBook
ISBN: 978-1-4614-0872-7
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark
This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
Zielgruppe
Research
Autoren/Hrsg.
Weitere Infos & Material
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.
