Alpert / Mehta / Sapatnekar Handbook of Algorithms for Physical Design Automation

Erscheinungsjahr 2008
ISBN: 978-1-4200-1348-1
Verlag: Taylor & Francis
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 1024 Seiten

The physical design flow of any project depends upon the size of the design, the technology, the number of designers, the clock frequency, and the time to do the design. As technology advances and design-styles change, physical design flows are constantly reinvented as traditional phases are removed and new ones are added to accommodate changes in technology.
Handbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on the major technical milestones in the history of physical design automation.
Although several books on this topic are currently available, most are either too broad or out of date. Alternatively, proceedings and journal articles are valuable resources for researchers in this area, but the material is widely dispersed in the literature. This handbook pulls together a broad variety of perspectives on the most challenging problems in the field, and focuses on emerging problems and research results.

Zielgruppe

Computer scientists, circuit designers, and post-graduate students and researchers in computer science.

Autoren/Hrsg.

Alpert, Charles J.

Mehta, Dinesh P.

Sapatnekar, Sachin S.

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Introduction
Introduction to Physical Design, C.J. Alpert, D.P. Mehta, and S.S. Sapatnekar
Layout Synthesis: A Retrospective, R.H.J.M. Otten
Metrics Used in Physical Design, F. Liu
Foundations
Basic Data Structures, D.P. Mehta and H. Zhou
Basic Algorithmic Techniques, V. Khandelwal and A. Srivastava
Optimization Techniques for Circuit Design Applications, Z.-Q. (Tom) Luo
Partitioning and Clustering, D. Kucar
Floorplanning
Floorplanning: Early Research, S. Sur-Kolay
Slicing Floorplans, T.-C. Wang and M.D.F. Wong
Floorplan Representations, E.F.Y. Young
Packing Floorplan Representations, T.-C. Chen and Y.-W. Chang
Recent Advances in Floorplanning, D.P. Mehta and Y. Feng
Industrial Floorplanning and Prototyping, L.K. Scheffer
Placement
Placement: Introduction/Problem Formulation, G.-J. Nam and P.G. Villarrubia
Partitioning-BasedMethods, J.A. Roy and I.L. Markov
Placement Using Simulated Annealing, W. Swartz
Analytical Methods in VLSI Placement, U. Brenner and J. Vygen
Force-Directed and Other Continuous Placement Methods, A. Kennings and K. Vorwerk
Enhancing Placement with Multilevel Techniques, J. Cong and J.R. Shinnerl
Legalization and Detailed Placement, A.R. Agnihotri and P.H. Madden
Timing-Driven Placement, D.Z. Pan, B. Halpin, and H. Ren
Congestion-Driven Physical Design, S.N. Adya and X. Yang
Net Layout and Optimization
Global-Routing Formulation andMaze Routing, M.M. Ozdal and M.D.F. Wong
Minimum Steiner Tree Construction, G. Robins and A. Zelikovsky
Timing-Driven Interconnect Synthesis, J. Hu, G. Robins, and C.N. Sze
Buffer Insertion Basics, J. Hu, Z. Li, and S. Hu
Generalized Buffer Insertion, M. Hrki´c and J. Lillis
Buffering in the Layout Environment, J. Hu and C.N. Sze
Wire Sizing, S. Roy and C.C.-P. Chen
Routing Multiple Signal Nets
Estimation of Routing Congestion, R.S. Shelar and P. Saxena
Rip-Up and Reroute, J.S. Salowe
Optimization Techniques in Routing, C. Albrecht
Global Interconnect Planning, C.-K. Koh, E.F.Y. Young, and Y.-W. Chang
Coupling Noise, R. Panda, V. Zolotov, and M. Becer
Manufacturability and Detailed Routing
Modeling and Computational Lithography, F.M. Schellenberg
CMP Fill Synthesis: A Survey of Recent Studies, A.B. Kahng and K. Samadi
Yield Analysis and Optimization, P. Gupta and E. Papadopoulou
Manufacturability-Aware Routing, M. Cho, J. Mitra, and D.Z. Pan
Physical Synthesis
PDS (Placement-Driven Synthesis) Design Closure Tool, C.J. Alpert, N. Hieter, A. Mets, R. Puri, L. Reddy, H. Ren, and L. Trevillyan
X Architecture Place and Route: Physical Design for the X Interconnect
Architecture, S. Teig, A. Hetzel, J. Ganley, J. Frankle, and A. Fujimura
Designing Large Global Nets
Inductance Effects in Global Nets, Y.I. Ismail
Clock Network Design: Basics, C.C.-N. Chu and M. Pan
Practical Issues in Clock Network Design, C.C.-N. Chu and M. Pan
Power Grid Design, H. Su and S. Nassif
Physical Design for Specialized Technologies
Field-ProgrammableGate Array Architectures, S.J.E. Wilton, N.C.K. Choy, S. Chin,
and K.K.W. Poon
FPGA Technology Mapping, Placement, and Routing, K. Bazargan
Physical Design for 3D Circuits, K. Bazargan and S.S. Sapatnekar
Index