Branch-and-bound search has been known for a long time and has been widely used in solving a variety of problems in computer-aided design (CAD) and many important optimization problems.
In many applications, the classic branch-and-bound search methods perform duplications of computations, or rely on the search decision trees which keep track of the branch-and-bound search processes. In CAD and many other technical fields, the computational cost of constructing branch-and-bound search decision trees in solving large scale problems is prohibitive and duplications of computations are intolerable. Efficient branch-and-bound methods are needed to deal with today's computational challenges. Efficient branch-and-bound methods must not duplicate computations.
Efficient Branch and Bound Search with Application to Computer-AidedDesign
describes an efficient branch-and-bound method for logic justification, which is fundamental to
automatic test patterngeneration
(ATPG), redundancy identification, logic synthesis, minimization, verification, and other problems in CAD. The method is called
justification equivalence
, based on the observation that justification processes may share identical subsequent search decision sequences. With justification equivalence, duplication of computations is avoided in the dynamic branch-and-bound search process without using search decision trees.
Efficient Branch and Bound Search with Application to Computer-AidedDesign
consists of two parts. The first part, containing the first three chapters, provides the theoretical work. The second part deals with applications, particularly ATPG for sequential circuits.
This book is particularly useful to readers who are interested in the design and test of digital circuits.
Bushnell
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Weitere Infos & Material
I Theory.- 1 Introduction.- 2 Justification Equivalence.- 3 Justification in Finite State Space.- II Applications.- 4 Sequential Circuit Test Generation.- 5 Fault Effects.- 6 The Sest Algorithm.- 7 Experimental Results.- 8 Redundancy Identification.- 9 Logic Verification.- 10 Conclusion.- A Sest User’s Guide.- A.1 Introduction.- A.2 Command Synopsis.- A.3 Options.- A.4 Inputs and Outputs.- A.5 Output Files.- A.6 Example.- A.7 Down-Loading SEST from the Disk.- A.8 Reporting Bugs.- A.9 Author.- References.
