Fujiwara Code Design for Dependable Systems

Theory and Practical Applications
1. Auflage 2006
ISBN: 978-0-471-79273-4
Verlag: John Wiley & Sons
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 720 Seiten, E-Book

Theoretical and practical tools to master matrix code designstrategy and technique
Error correcting and detecting codes are essential to improvingsystem reliability and have popularly been applied to computersystems and communication systems. Coding theory has been studiedmainly using the code generator polynomials; hence, the codes aresometimes called polynomial codes. On the other hand, the codesdesigned by parity check matrices are referred to in this book asmatrix codes. This timely book focuses on the design theory formatrix codes and their practical applications for the improvementof system reliability. As the author effectively demonstrates,matrix codes are far more flexible than polynomial codes, as theyare capable of expressing various types of code functions.
In contrast to other coding theory publications, this one does notburden its readers with unnecessary polynomial algebra, but ratherfocuses on the essentials needed to understand and take fulladvantage of matrix code constructions and designs. Readers arepresented with a full array of theoretical and practical tools tomaster the fine points of matrix code design strategy andtechnique:
* Code designs are presented in relation to practical applications,such as high-speed semiconductor memories, mass memories of disksand tapes, logic circuits and systems, data entry systems, anddistributed storage systems
* New classes of matrix codes, such as error locating codes, spottybyte error control codes, and unequal error control codes, areintroduced along with their applications
* A new parallel decoding algorithm of the burst error controlcodes is demonstrated
In addition to the treatment of matrix codes, the author providesreaders with a general overview of the latest developments andadvances in the field of code design. Examples, figures, andexercises are fully provided in each chapter to illustrate conceptsand engage the reader in designing actual code and solving realproblems. The matrix codes presented with practical parametersettings will be very useful for practicing engineers andresearchers. References lead to additional material so readers canexplore advanced topics in depth.
Engineers, researchers, and designers involved in dependable systemdesign and code design research will find the unique focus andperspective of this practical guide and reference helpful infinding solutions to many key industry problems. It also can serveas a coursebook for graduate and advanced undergraduate students.

Autoren/Hrsg.

Fujiwara, Eiji

Inhaltsverzeichnis

Preface.
1. Introduction.
1.1 Faults and Failures.
1.2 Error Models.
1.3 Error Recovery Techniques for Dependable Systems.
1.4 Code Design Process for Dependable Systems.
References.
2. Mathematical Background and Matrix Codes.
2.1 Introduction to Algebra.
2.2 Linear Codes.
2.3 Basic Matrix Codes.
Exercises.
References.
3. Design Techniques for Matrix Codes.
3.1 Minimum-Weight & Equal-Weight-Row Codes.
3.2 Odd-Weight-Column Codes.
3.3 Even-Weight-Row Codes.
3.4 Odd-Weight-Row Codes.
3.5 Rotational Codes.
Exercises.
References.
4. Codes for High-Speed Memories I: Bit Error Control Codes.
4.1 Modified Hamming SEC-DED Codes.
4.2 Modified Double-Bit Error Correcting BCH Codes.
4.3 On-Chip ECCs.
Exercises.
References.
5. Codes for High-Speed Memories II: Byte Error Control Codes.
5.1 Single-Byte Error Correcting (SbEC) Codes.
5.2 Single-Byte Error Correcting and Double-Byte Error Detecting (SbEC-DbED) Codes.
5.3 Single-Byte Error Correcting and Single p-Byte within a Block Error Detecting (SbEC-Spb=BED) Codes.
Exercises.
References.
6. Codes for High-Speed Memories III: Bit / Byte Error Control Codes.
6.1 Single-Byte / Burst Error Detecting SEC-DED Codes.
6.2 Single-Byte Error Correcting and Double-Bit Error Detecting (SbEC-DED) Codes.
6.3 Single-Byte Error Correcting and Double-Bit Error Correcting (SbEC-DEC) Codes.
6.4 Single-Byte Error Correcting and Single-Byte Plus Single-Bit Error Detecting (SbEC-(SbdS)ED) Codes.
Exercises.
References.
7. Codes for High-Speed Memories IV: Spotty Byte Error Control Codes.
7.1 Spotty Byte Errors.
7.2 Single Spotty Byte Error Correcting (St=bEC) Codes.
7.3 Single Spotty Byte Error Correcting and Single-Byte Error Detecting (St=bEC-SbED) Codes.
7.4 Single Spotty Byte Error Correcting and Double Spotty Byte Error Detecting (St=bEC-Dt=bED) Codes.
7.5 A General Class of Spotty Byte Error Control Codes.
Exercises.
References.
8. Paralled Decoding for Burst / Byte Error Control Codes.
8.1 Parallel Decoding Burst Error Control Codes.
8.2 Parallel Decoding Cyclic Burst Error Correcting Codes.
8.3 Transient Behavior of Parallel Encoder / Decoder Circuits of Error Control Codes.
Exercises.
References.
9. Codes for Error Location: Error Locating Codes.
9.1 Error Location of Faulty Packages and Faulty Chips.
9.2 Block Error Locating (Sb=pbEL) Codes.
9.3 Single-Bit Error Correcting and Single-Block Error Locating (SEC-Sb=pbEL) Codes.
9.4 Single-Bit Error Correcting and Single-Byte Error Locating (SEC-Se=bEL) Codes.
9.5 Burst Error Locating Codes.
9.6 Code Conditions for Error Locating Codes.
10. Codes for Unequal Error Control / Protection (UEC / UEP).
10.1 Error Models for UEC Codes and UEP Codes.
10.2 Fixed-Byte Error Control UEC Codes.
10.3 Burst Error Control UEC / UEP Codes.
10.4 Application of the UEC / UEP Codes.
Exercises.
References.
11. Codes for Mass Memories.
11.1 Tape Memory Codes.
11.2 Magnetic Disk Memory Codes.
11.3 Optical Disk Memory Codes.
Exercises.
References.
12. Coding for Logic and System Design.
12.1 Self-checking Concept.
12.2 Self-testing Checkers.
12.3 Self-checking ALU.
12.4 Self-checking Design for Computer Systems.
Exercises.
References.
13. Codes for Data Entry Systems.
13.1 M-Ary Asymmetric Errors in Data Entry Systems.
13.2 M-Ary Asymmetric Symbol Error Correcting Codes.
13.3 Nonsystematic M-Ary Asymmetric Error Correcting Codes with Deletion / Insertion / Adjacent-Symbol-Transposition Error Correction Capabilities.
13.4 Codes for Two-Dimentional Matrix Symbols.
Exercises.
References.
14. Codes for Multiple / Distributed Storage Systems.
14.1 MDS Array Codes Tolerating Multiple-Disk Failures.
14.2 Codes for Distributed Storage Systems.
Exercises.
References.
Index.

Über Autor(innen)

EIJI FUJIWARA, PhD, is Professor at the Tokyo Institute of Technology. His research interests include design theory for error control codes, dependable systems, and error tolerant data compression.