Köhler Enhancing Embedded Systems Simulation

A Chip-Hardware-in-the-Loop Simulation Framework
2011
ISBN: 978-3-8348-9916-3
Verlag: Vieweg & Teubner
Format: PDF
Kopierschutz: Wasserzeichen (»Systemvoraussetzungen)

E-Book, Englisch, 224 Seiten, eBook

Christian Köhler covers the connection between µC and simulation, the interface abstraction as well as the analysis and optimization of coupling systems with the Chip-Hardware-in-the-Loop Simulation (CHILS) approach. He develops the hardware to simulation coupling system with a focus on less hardware effort, the capabilities to couple with different simulation environments, and the efficiency of coupling. Furthermore, the author presents existing concepts to simulate complex systems and compares them with the new approach.

Dr. rer. nat. Christian Köhler completed his doctoral thesis under the supervision of Prof. Dr. sc. techn. Andreas Herkersdorf at the Institute for Integrated Systems, Department of Electrical Engineering and Information Technology, Technische Universität München (TUM).

Zielgruppe

Research

Autoren/Hrsg.

Köhler, Christian

Inhaltsverzeichnis

1;Acknowledgment;6
2;Contents;8
3;List of Figures;11
4;List of Tables;14
5;Acronyms;16
6;1 Introduction;22
6.1;1.1 Motivation;22
6.2;1.2 Objective of the Thesis;23
6.3;1.3 Thesis Organization;24
7;2 Related Work and Work Hypothesis;26
7.1;2.1 Work Hypothesis;26
7.2;2.2 Basics;29
7.2.1;2.2.1 Motivation for Modelling and Simulation;30
7.2.2;2.2.2 Modelling Basics;32
7.2.3;2.2.3 Simulation Systems;33
7.2.3.1;2.2.3.1 Continuous Simulation;34
7.2.3.2;2.2.3.2 Discrete Simulation;35
7.3;2.3 Possibilities of Hardware-Simulation-Coupling;36
7.3.1;2.3.1 Motivation for Hardware-in-the-Loop;37
7.3.2;2.3.2 Commercial Hardware-in-the-Loop Solutions;38
7.3.2.1;2.3.2.1 MathWorks™;39
7.3.2.2;2.3.2.2 dSPACE;39
7.3.2.3;2.3.2.3 Modelica/Dymola;40
7.3.2.4;2.3.2.4 National Instruments;40
7.3.2.5;2.3.2.5 Visual Solutions;41
7.3.2.6;2.3.2.6 ETAS;41
7.3.3;2.3.3 Non-Commercial Hardware-in-the-Loop Solutions;41
7.3.3.1;2.3.3.1 University of South Carolina – Virtual Test Bed;41
7.3.3.2;2.3.3.2 ETH Zürich – Generic Hardware-in-the-loop Framework;42
7.3.3.3;2.3.3.3 University of Twente – Borderc project;42
7.3.3.4;2.3.3.4 University of Karlsruhe – COMPASS;42
7.3.4;2.3.4 Coupling Concepts;42
7.4;2.4 Additional Concepts;44
7.4.1;2.4.1 System-Simulation;44
7.4.2;2.4.2 Software-in-the-Loop Simulation;44
7.4.3;2.4.3 Hardware-in-the-Loop Simulation;45
7.4.4;2.4.4 Emulation and Emulator;46
7.5;2.5 Comparison of the Concepts;47
7.6;2.6 Subproblems of Hardware-Simulation-Coupling;47
7.6.1;2.6.1 Connection between Hardware and Simulation;48
7.6.2;2.6.2 Interface Abstraction;48
7.6.3;2.6.3 Event Exchange Optimization;48
8;3 Connection between Hardware and Simulation;50
8.1;3.1 Basics;50
8.1.1;3.1.1 Simulator Coupling and Co-Simulation;50
8.1.2;3.1.2 Synchronization of Co-Simulations;52
8.2;3.2 Related Work;53
8.3;3.3 Exchange of Events between Microcontroller and Simulation;56
8.3.1;3.3.1 Continuous Simulation;57
8.3.1.1;3.3.1.1 Basic Coupling Principles;57
8.3.2;3.3.2 Event Discrete Simulation;59
8.3.2.1;3.3.2.1 Basic Coupling Principles;60
8.3.3;3.3.3 Conclusions;62
8.3.3.1;3.3.3.1 Levels of Simulator Coupling;63
8.4;3.4 CHILS Event Exchange Mechanism;63
8.5;3.5 E.ects Caused by Coupling;66
8.5.1;3.5.1 Measurement of the Timing Difference;66
8.5.1.1;3.5.1.1 System Timer (STM);67
8.5.1.2;3.5.1.2 GPTA;67
8.5.2;3.5.2 Causes for the Timing Di.erence;69
8.5.2.1;3.5.2.1 Additional Instructions;69
8.5.2.2;3.5.2.2 Delayed Suspend;71
8.5.2.3;3.5.2.3 Pipelining;71
8.5.2.4;3.5.2.4 Caching;72
8.5.3;3.5.3 Possibilities for Compensation;72
8.6;3.6 Summary;74
9;4 Interfaces between Microcontroller and Environment;76
9.1;4.1 Related Work;76
9.2;4.2 Interface Modelling and Abstraction;79
9.2.1;4.2.1 Interface Abstraction;80
9.2.2;4.2.2 Interface Representation;80
9.2.2.1;4.2.2.1 Digital Interfaces;82
9.2.2.2;4.2.2.2 Analogue Interfaces;82
9.2.2.3;4.2.2.3 Communication Interfaces;83
9.3;4.3 Summary;85
10;5 Optimization – Coupling System Analysis;86
10.1;5.1 Related Work;87
10.2;5.2 Basics;88
10.3;5.3 Formal De.nitions;89
10.3.1;5.3.1 Transparency and Fidelity Deffnition;89
10.3.2;5.3.2 Application of the Coupling System Fidelity;95
10.4;5.4 Example;95
10.5;5.5 Comparison of Di.erent Coupling Systems;98
10.5.1;5.5.1 Simulation Scenario;99
10.5.2;5.5.2 Interpretation of Data Sheets;99
10.5.3;5.5.3 Scenarios;101
10.5.4;5.5.4 CHILS vs. DeskPOD™;102
10.5.4.1;5.5.4.1 DeskPOD™ Hardware;102
10.5.4.2;5.5.4.2 Scenarios;103
10.5.5;5.5.5 CHILS vs. dSPACE;103
10.5.5.1;5.5.5.1 dSPACE Hardware;103
10.5.5.2;5.5.5.2 Scenarios;104
10.5.6;5.5.6 Comparison Results;104
10.6;5.6 Summary;106
11;6 Optimization – Analysis of the Real System and Environment;107
11.1;6.1 Analysis of Algorithms;107
11.1.1;6.1.1 Related Works;108
11.1.2;6.1.2 Numerical Basics;109
11.1.2.1;6.1.2.1 Error Propagation;109
11.1.3;6.1.3 Arithmetic Basic Operations;110
11.1.3.1;6.1.3.1 Combination of Arithmetic Basic Operations;111
11.1.4;6.1.4 Algorithm Analysis Process;112
11.1.4.1;6.1.4.1 CFG-DFG Analysis;113
11.1.4.2;6.1.4.2 Training Set;117
11.1.4.3;6.1.4.3 Complexity of Subgraph Training Set Calculation;118
11.2;6.2 Classi.cation of Algorithms;118
11.2.1;6.2.1 Related Work;119
11.2.2;6.2.2 Classi.cation Process;120
11.2.2.1;6.2.2.1 Graph Matching;120
11.2.2.2;6.2.2.2 Recombination;122
11.2.2.3;6.2.2.3 Experimental Results;123
11.3;6.3 Analysis and Classi.cation of Systems;124
11.3.1;6.3.1 Stability of Linear Time Invariant Systems;126
11.3.2;6.3.2 Stability of Nonlinear Time Invariant Systems;127
11.4;6.4 General Analysis;129
11.4.1;6.4.1 Stability of Control Loops;129
11.4.2;6.4.2 Example;130
11.4.3;6.4.3 Control Path Analysis;131
11.4.4;6.4.4 Control Analysis – Analytical;131
11.4.5;6.4.5 Control Loop Analysis;131
11.4.6;6.4.6 Control Analysis – Numerical;132
11.5;6.5 Summary;134
12;7 Optimization – Runtime Analysis;137
12.1;7.1 Metric Basics;137
12.1.1;7.1.1 Events;137
12.1.2;7.1.2 Simulation Coupling;138
12.2;7.2 Metric De.nitions;138
12.2.1;7.2.1 Execution Time Accuracy;138
12.2.2;7.2.2 Event Distribution Accuracy;139
12.2.3;7.2.3 Event Occurrence Accuracy;141
12.3;7.3 Example;142
12.4;7.4 Summary;144
13;8 CHILS Framework – Concept;146
13.1;8.1 Functionality – CHILS Basics;146
13.1.1;8.1.1 Data Exchange and Synchronization;146
13.1.2;8.1.2 Interface Abstraction;148
13.2;8.2 Microcontroller Requirements;149
13.2.1;8.2.1 Microcontroller Adaptations for Future Versions;149
13.2.1.1;8.2.1.1 Microcontroller Peripherals;149
13.2.1.2;8.2.1.2 Monitor Context;150
13.3;8.3 Range of Applications;151
13.3.1;8.3.1 CHILS and the V-Model;151
13.3.2;8.3.2 Rapid Control Prototyping;151
13.3.3;8.3.3 Test Applications;152
13.3.4;8.3.4 Estimation of the Real-Time Capability of Software with CHILS;153
13.4;8.4 Features;153
13.4.1;8.4.1 Simulation Coupling – CHILS-API;153
13.4.2;8.4.2 Device Coupling – DAS Architecture;155
13.4.3;8.4.3 Debugger Support – MCD-API;155
13.4.4;8.4.4 Tools for Coupling Optimization;155
13.4.4.1;8.4.4.1 Coupling System Analysis;155
13.4.4.2;8.4.4.2 Algorithm Analysis;156
13.4.4.3;8.4.4.3 CHILS Runtime Pro.ling;157
13.4.4.4;8.4.4.4 CHILS Simulation Step Size Calculation;158
13.5;8.5 Optimization Flow;158
13.6;8.6 Summary;160
14;9 CHILS Framework – Classi.cation;161
14.1;9.1 Software Models on Di.erent Levels of Abstraction;161
14.1.1;9.1.1 Functional Simulation;163
14.1.2;9.1.2 Instruction Accurate Simulation;163
14.1.3;9.1.3 Transactional Level with/without Time;164
14.1.4;9.1.4 Cycle Accurate Models;164
14.1.5;9.1.5 Register Transfer Level;164
14.1.6;9.1.6 Physical Level;165
14.2;9.2 Embedding of Hardware in Simulations;165
14.2.1;9.2.1 Original Microcontroller;165
14.2.1.1;9.2.1.1 Pin-Based Connection;165
14.2.1.2;9.2.1.2 Embedding via Communication Interface;167
14.2.2;9.2.2 Emulation;169
14.3;9.3 Comparison;170
14.4;9.4 CHILS Performance and Accuracy;177
14.4.1;9.4.1 CHILS Accuracy;177
14.4.2;9.4.2 CHILS Performance;177
14.5;9.5 Summary;180
15;10 CHILS Framework – Applications;181
15.1;10.1 SystemC-Coupling;181
15.1.1;10.1.1 Virtual Peripheral Extension;184
15.2;10.2 Matlab/Simulink-Coupling;186
15.2.1;10.2.1 CHILS-Demonstration Platform;188
15.2.1.1;10.2.1.1 Results;189
16;11 Summary and Outlook;192
16.1;11.1 Summary;192
16.1.1;11.1.1 Connection between Hardware and Simulation;192
16.1.2;11.1.2 Interface Abstraction;193
16.1.3;11.1.3 Event Exchange Optimization;193
16.1.4;11.1.4 CHILS Framework;194
16.1.5;11.1.5 Conclusion;195
16.2;11.2 Outlook and Future Work;195
16.2.1;11.2.1 Driver Support;195
16.2.2;11.2.2 Hardware Support;196
16.2.3;11.2.3 Microcontroller Extensions;196
16.2.4;11.2.4 Integration into Commercial Solutions;197
16.2.5;11.2.5 Coupling System Analysis;197
16.2.6;11.2.6 Algorithm Analysis;197
17;A Formulas;198
17.1;A.1 Chapter 5;198
17.1.1;A.1.1 Fidelity Functions of System Comparison;198
18;B Tables;199
18.1;B.1 Chapter 3;199
18.1.1;B.1.1 Time Di.erence Measurement;199
18.1.2;B.1.2 Time Di.erence Measurement – dsync/isync;200
18.2;B.2 Chapter 5;201
18.2.1;B.2.1 Result Tables of System Comparison;201
18.3;B.3 Chapter 9;203
18.3.1;B.3.1 Synthetic Simulation Performance;203
19;C Listings;205
19.1;C.1 Chapter 8;205
19.1.1;C.1.1 CHILS-API;205
19.2;C.2 Chapter 10;208
19.2.1;C.2.1 MATLAB®/Simulink® s-function;208
19.2.2;C.2.2 SystemC;213
20;D Datasheets;217
20.1;D.1 Chapter 2;217
20.2;D.2 Chapter 5;218
20.2.1;D.2.1 DeskPOD™ Datasheet;218
20.2.2;D.2.2 dSpace Datasheets;218
21;Bibliography;220
22;Glossary;231

Über Autor(innen)

Dr. rer. nat. Christian Köhler completed his doctoral thesis under the supervision of Prof. Dr. sc. techn. Andreas Herkersdorf at the Institute for Integrated Systems, Department of Electrical Engineering and Information Technology, Technische Universität München (TUM).