Lysaght / Rosenstiel New Algorithms, Architectures and Applications for Reconfigurable Computing

1. Auflage 2005
ISBN: 978-1-4020-3128-1
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 315 Seiten, eBook

New Algorithms, Architectures and Applications for Reconfigurable Computing consists of a collection of contributions from the authors of some of the best papers from the Field Programmable Logic conference (FPL’03) and the Design and Test Europe conference (DATE’03). In all, seventy-nine authors, from research teams from all over the world, were invited to present their latest research in the extended format permitted by this special volume. The result is a valuable book that is a unique record of the state of the art in research into field programmable logic and reconfigurable computing. The contributions are organized into twenty-four chapters and are grouped into three main categories: architectures, tools and applications. Within these three broad areas the most strongly represented themes are coarse-grained architectures; dynamically reconfigurable and multi-context architectures; tools for coarse-grained and reconfigurable architectures; networking, securityand encryption applications.Field programmable logic and reconfigurable computing are exciting research disciplines that span the traditional boundaries of electronic engineering and computer science. When the skills of both research communities are combined to address the challenges of a single research discipline they serve as a catalyst for innovative research. The work reported in the chapters of this book captures that spirit of that innovation.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Lysaght, Patrick

Rosenstiel, Wolfgang

Inhaltsverzeichnis

Architectures.- Extra-dimensional Island-Style FPGAs.- A Tightly Coupled VLIW/Reconfigurable Matrix and its Modulo Scheduling Technique.- Stream-based XPP Architectures in Adaptive System-on-Chip Integration.- Core-Based Architecture for Data Transfer Control in SoC Design.- Customizable and Reduced Hardware Motion Estimation Processors.- Methodologies and Tools.- Enabling Run-time Task Relocation on Reconfigurable Systems.- A Unified Codesign Environment.- Mapping Applications to a Coarse Grain Reconfigurable System.- Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture.- Run-time Defragmentation for Dynamically Reconfigurable Hardware.- Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems.- A Low Energy Data Management for Multi-Context Reconfigurable Architectures.- Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements Tools and a Case Study.- Applications.- Design Flow for a Reconfigurable Processor.- IPsec-Protected Transport of HDTV over IP.- Fast, Large-scale String Match for a 10 Gbps FPGA-based NIDS.- Architecture and FPGA Implementation of a Digit-serial RSA Processor.- Division in GF(p) for Application in Elliptic Curve Cryptosystems on Field Programmable Logic.- A New Arithmetic Unit in GF(2M) for Reconfigurable Hardware Implementation.- Performance Analysis of SHACAL-1 Encryption Hardware Architectures.- Security Aspects of FPGAs in Cryptographic Applications.- Bioinspired Stimulus Encoder for Cortical Visual Neuroprostheses.- A Smith-Waterman Systolic Cell.- The Effects of Polynomial Degrees.

Leseproben

11.3 The Byte Code Compiler (p.137- 138)

The Byte Code Compiler is a very important feature of the VHBC approach, because it provides the means to compile working hardware designs, coded as a VHDL description, into a portable and efficient VHBC representation, thus removing the need for redesigning working hardware projects. The tool flow within the VHDL compiler can basically be divided into three main stages, the hardware synthesis, the net list to byte code conversion and the byte code optimization and scheduling.

In the first stage the VHDL description is compiled into a net list of standard components and standard logic optimization is performed upon it, resulting in an optimized net list. The design of the compiler chain can be streamlined through the use of off-the-shelf hardware synthesis tools. Current implementations of the VHDL compiler make e.g. use of the FPGAExpress tool from Synopsis. These tools produce the anticipated code using a fairly standardized component library, as in the case of FPGA Express the SimPrim library from Xilinx. The resulting output of the first stage is converted to structural VHDL and passed on to the second stage. Most standard industry VHDL compilers with a support for FPGAs design readily provide the functionality needed for this step and can therefore be applied.

In the second stage the components of the net list are substituted by VHBC fragments to form aVHBCinstruction stream. Before, however, the components are mapped to a VHBC representation, the net list is analyzed and optimized for VHBC. The optimization is necessary because commercial compilers targeting FPGAs usually output designs which contain large amounts of buffers to enhance signal integrity otherwise impaired by the routing of the signals. Furthermore, compilers show a tendency towards employing logic representations based on NAND or NOR gates, which are more ef.cient when cast into silicon.

However, the resulting logic structure is more complex, revealing higher levels of logic. The code fragments used for substituting the logic components are based on predefined, general implementations of the latter in VHBC and are adjusted according to the data flow found in the structural description from the first phase, thus registers are allocated and the instructions are sequenced according to the data dependencies inherent.

In the third stage the byte code sequence is optimized and scheduled into blocks of independent instructions. First of all the data flow graph of the entire design is constructed, which is possible due to the lack of control flow instructions such as jumps. The code fragments introduced in the second stage are very general, so the resulting code gives a lot of room to code optimization techniques. One such technique is dead code elimination, which removes unnecessary instructions. The code is further optimized by applying predefined code substitution rules along the data paths, such as XOR extraction or doublenegation removal, to reduce the number of instructions and compact the code.

The thus optimized code is scheduled using a list based scheduling scheme [14]. The objective of the scheduling is to group the instructions into code blocks such that the number of code blocks is minimal and the number of instructions per code block is evenly distributed among all code blocks. Furthermore, the time of data not being used, i.e. the number of clock cycles between the calculation of a datum and its use in another operation should be minimal. The scheduled code is then converted to the VHBC image format and the compiler flow concludes.