Muttoo System and Architecture

Proceedings of CSI 2015
1. Auflage 2018
ISBN: 978-981-10-8533-8
Verlag: Springer Singapore
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 732, 333 Seiten, eBook

Reihe: Advances in Intelligent Systems and Computing

This book comprises the select proceedings of the annual convention of the Computer Society of India. Divided into 10 topical volumes, the proceedings present papers on state-of-the-art research, surveys, and succinct reviews. The volumes cover diverse topics ranging from parallel processing to system buses, and from computer architecture to VLIW (very long instruction word). This book focuses on systems and architecture. It aims at informing the readers about those attributes of a system visible to a programmer. This book also deals with various innovations and improvements in computing technologies to improve the size, capacity and performance of modern-day computing systems. The contents of this book will be useful to professionals and researchers alike.

Zielgruppe

Research

Autoren/Hrsg.

Muttoo, Sunil Kumar

Inhaltsverzeichnis

1;Preface;6
2;The Organization of CSI-2015;9
3;Contents;11
4;About the Editor;14
5;1 A Mathematical AI-Based Diet Analysis and Transformation Model;15
5.1;Abstract;15
5.2;1 Introduction;15
5.3;2 Problem Statement;16
5.4;3 Energy Requirements and Its Evaluation;17
5.4.1;3.1 Nutrients Consideration;17
5.5;4 Fuzzy Arithmetic and Computation;17
5.5.1;4.1 Preliminaries;17
5.6;5 Tabu Search Background;18
5.7;6 Proposed Work;18
5.7.1;6.1 Diet Analysis Module;19
5.7.2;6.2 Optimization Module;19
5.7.3;6.3 Diet Transformation Module;19
5.8;7 Concluding Discussion;20
5.9;Declaration;21
5.10;References;21
6;2 Energy Efficient Measures for Sustainable Development of Data Centers;22
6.1;Abstract;22
6.2;1 Introduction;23
6.3;2 Scope of Energy Efficient Technologies and Techniques in Data Centers;24
6.4;3 Energy Saving in Electrical System;24
6.5;4 Cooling System;25
6.6;5 IT Equipment;27
6.7;6 Operation and Maintenance in Data Center;29
6.8;7 Conclusion;30
6.9;8 Future Scope;31
6.10;References;31
7;3 Analysis on Multiple Combinations of Series–Parallel Connections of Super Capacitors for Maximum Energy Transferring to Load in Minimum Time;33
7.1;Abstract;33
7.2;1 Introduction;33
7.2.1;1.1 Proposed Scheme;34
7.2.2;1.2 Basic Scheme;34
7.3;2 Case-1;36
7.4;3 Case-2;39
7.5;4 Case-3;41
7.6;5 Conclusion;45
7.7;References;46
8;4 Design and Simulation of OTA Using 45 nm Technology;47
8.1;Abstract;47
8.2;1 Introduction;47
8.3;2 Device Structure and Features;48
8.4;3 Operational Transconductance Amplifier;49
8.4.1;3.1 Results;51
8.5;4 Conclusion;52
8.6;References;52
9;5 Design and Analysis of Microstrip Patch Antenna Using DRAF;54
9.1;Abstract;54
9.2;1 Introduction;55
9.3;2 Antenna Design;55
9.3.1;2.1 Design of Microstrip Triangular Patch Antenna with Side Length a = 25 mm;55
9.3.2;2.2 Design of Microstrip Triangular Patch Antenna with Side Length a = 30 mm;57
9.4;3 Simulated Results;58
9.5;4 Conclusion;61
9.6;Acknowledgements;61
9.7;References;62
10;6 Principal Component Analysis-Based Block Diagonalization Precoding Algorithm for MU-MIMO System;63
10.1;Abstract;63
10.2;1 Introduction;63
10.2.1;1.1 Organization;65
10.2.2;1.2 Notation;65
10.3;2 MU-MIMO System Model;65
10.4;3 Proposed PCA-Based Precoding Algorithm;66
10.5;4 Performance Analysis;69
10.6;5 Conclusion;70
10.7;References;71
11;7 Low-Power High-Performance Multitransform Architecture Using Run-Time Reconfigurable Adder for FPGA and ASIC Implementation;72
11.1;Abstract;72
11.2;1 Introduction;73
11.3;2 Multitransform Architecture;73
11.4;3 Proposed Adder;74
11.5;4 Performance Evaluation and Comparison;77
11.5.1;4.1 FPGA Implementation;77
11.5.2;4.2 ASIC Implementation;78
11.6;5 Conclusion and Future Scope;80
11.7;Acknowledgements;80
11.8;References;80
12;8 A Review of Dynamic Scheduling Algorithms for Homogeneous and Heterogeneous Systems;82
12.1;Abstract;82
12.2;1 Introduction;82
12.3;2 Homogeneous and Heterogeneous Systems;84
12.3.1;2.1 Heterogeneous System;84
12.3.2;2.2 Homogeneous System;84
12.4;3 Review of Dynamic Scheduling Algorithms (DSA);85
12.4.1;3.1 The Earliest Time First (ETF) Algorithm;85
12.4.2;3.2 Dynamic Level Scheduling (DLS) Algorithm;85
12.4.3;3.3 The Earliest Deadline First (EDF) Algorithm;86
12.4.4;3.4 Online Scheduling of Dynamic Task Graph (OSDTG);86
12.4.5;3.5 Dynamic Load Balancing Using Task-Transfer Probabilities (DLBTTP);86
12.4.6;3.6 Dynamic Task Scheduling (DTS) Algorithm;86
12.4.7;3.7 DLS Algorithm with Genetic Operators (DLSAGO);87
12.4.8;3.8 Dynamic Task Graph Scheduling with Fault-Tolerant (FTDTGS);87
12.4.9;3.9 DTS with Load Balancing (DTSLB);87
12.4.10;3.10 Dynamic Load Balancing Using Genetic Algorithms (DLBGA);87
12.4.11;3.11 Parallel Genetic Algorithms for Heterogeneous (PGAH);88
12.4.12;3.12 Global Scheduling for Mixed-Critically (GSMC);88
12.4.13;3.13 The Response Time Analysis of Global Fixed-Priority (RTAGFP);88
12.4.14;3.14 New Response Time Bounds for Fixed Priority (RTBFP);88
12.4.15;3.15 Load-Based Schedulability Analysis of Certificate Mixed-Criticality System (LBSCMCS);90
12.5;4 Comparison of Dynamic Scheduling Algorithms on HMS and HTS;90
12.6;5 Conclusion and Future Work;91
12.7;References;91
13;9 Effective Information Retrieval Algorithm for Linear Multiprocessor Architecture;93
13.1;Abstract;93
13.2;1 Introduction;93
13.3;2 The LCQ Server;95
13.4;3 System Model;96
13.4.1;3.1 The Proposed Algorithm;97
13.5;4 Result and Discussion;100
13.6;5 Conclusion;100
13.7;References;101
14;10 Design of Energy-Efficient Random Access Memory Circuit Using Low-Voltage CMOS and High-Speed Transreceiver Logic-I I/O Standard on 28 nm FPGA;103
14.1;Abstract;103
14.2;1 Introduction;103
14.3;2 Block Diagram of Memory;104
14.3.1;2.1 Register Transfer Level Schematic of 64-Bit RAM;104
14.3.2;2.2 Top-Level View of Random Access Memory Package Pins;105
14.4;3 Analysis of Power;105
14.4.1;3.1 Power Consumption on 2.0 GHz Frequency;106
14.4.1.1;3.1.1 Using LVCMOS;106
14.4.1.2;3.1.2 HSTL-I;106
14.4.2;3.2 Power Consumption on 2.1 GHz Frequency;107
14.4.2.1;3.2.1 LVCMOS;107
14.4.2.2;3.2.2 HSTL-I;107
14.4.3;3.3 Power Consumption on 2.5 GHz Frequency;108
14.4.3.1;3.3.1 LVCMOS;108
14.4.3.2;3.3.2 HSTL-I;108
14.4.4;3.4 Power Consumption on 2.9 GHz Frequency;109
14.4.4.1;3.4.1 Using LVCMOS;109
14.4.4.2;3.4.2 Using HSTL-I;110
14.4.5;3.5 Power Consumption on 3.1 GHz Frequency;110
14.4.5.1;3.5.1 Using LVCMOS;110
14.4.5.2;3.5.2 HSTL-I;111
14.4.6;3.6 Power Consumption on 3.5 GHz Frequency;111
14.4.6.1;3.6.1 Using LVCMOS;111
14.4.6.2;3.6.2 HSTL-I;112
14.5;4 Conclusion;113
14.6;5 Future Scopes;113
14.7;References;113
15;11 Stub Series Terminal Logic-Based Low-Power Thermal-Aware Vedic Multiplier Design on 40-nm FPGA;115
15.1;Abstract;115
15.2;1 Introduction;116
15.2.1;1.1 Antyayor_Dasakepi_Sutra;116
15.3;2 Power and Thermal Analysis of Vedic Multiplier;116
15.3.1;2.1 Analysis of MAT, Junction Temperature, and Leakage Power;116
15.4;3 IO Standards;118
15.4.1;3.1 Power Analysis;118
15.4.2;3.2 Thermal Analysis;119
15.5;4 Conclusion;120
15.6;5 Future Scope;120
15.7;References;121
16;12 LVCMOS-Based Low-Power Thermal-Aware Energy-Proficient Vedic Multiplier Design on Different FPGAs;122
16.1;Abstract;122
16.2;1 Introduction;123
16.2.1;1.1 Example 1: Square of 8?;123
16.2.2;1.2 Example 2: Square of 992?;123
16.3;2 Power Scrutiny via Scaling Thermally;124
16.3.1;2.1 Power Scrutiny Using LVCMOS_12 I/O Standard;124
16.3.2;2.2 Power Scrutiny Using LVCMOS15 IO Standard;125
16.3.3;2.3 Power Scrutiny via LVCMOS12 I/O Standard;125
16.3.4;2.4 Power Scrutiny via LVCMOS I/O Set on 20 °C;126
16.3.5;2.5 Power Scrutiny via LVCMOS I/O Set on 30 °C;127
16.3.6;2.6 Power Scrutiny via LVCMOS I/O Set on 45 °C;127
16.4;3 Conclusion;128
16.5;4 Future Scope;128
16.6;References;128
17;13 Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA;130
17.1;Abstract;130
17.2;1 Introduction;131
17.3;2 Related Work;131
17.4;3 Pin-out Report;132
17.5;4 Timing Analysis;134
17.5.1;4.1 Worst-Case Slack in Timing Analysis of DES Algorithm;135
17.5.2;4.2 Best Achievable Time in Timing Analysis of DES Algorithm;135
17.5.3;4.3 Timing Errors in Timing Analysis of DES Algorithm;136
17.5.4;4.4 Timing Scores in Timing Analysis of DES Algorithm;136
17.6;5 Static Timing Analysis;137
17.6.1;5.1 Setup Paths in Static Timing Analysis;137
17.6.2;5.2 Hold Paths in Static Timing Analysis;138
17.6.3;5.3 Component Switching Limits;139
17.7;6 Timing Report;139
17.8;7 Mapping Report;140
17.8.1;7.1 Worst-Case Slack in Mapping Report of DES Algorithm;140
17.8.2;7.2 Best-Case Achievement in Mapping Report of DES Algorithm;141
17.8.3;7.3 Timing Errors in Mapping Report of DES Algorithm;141
17.8.4;7.4 Timing Score in Mapping Report of DES Algorithm;141
17.9;8 Generating Clock Report;142
17.10;9 Conclusion;143
17.11;10 Future Scope;143
17.12;References;144
18;14 Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA;145
18.1;Abstract;145
18.2;1 Introduction;146
18.3;2 Related Work;146
18.4;3 Objective;147
18.5;4 Results;149
18.5.1;4.1 High-Speed Low-Voltage Digitally Controlled Impedance;149
18.5.2;4.2 Low-Voltage Transistor Logic;149
18.5.3;4.3 Low-Voltage Complementary Metal Oxide Semiconductor;150
18.5.4;4.4 Peripheral Component Interconnect Extended;150
18.5.5;4.5 Gunning Transceiver Logic;151
18.5.6;4.6 High-Speed Transistor Logic I;151
18.5.7;4.7 High-Speed Transceiver Logic IV;152
18.5.8;4.8 Stub Series Terminated Logic_II_Digitally Controlled Impedance;152
18.5.9;4.9 Low-Voltage Digitally Controlled Impedance_15;153
18.5.10;4.10 Peripheral Component Interconnect;153
18.6;5 Conclusion;155
18.7;6 Future Scopes;155
18.8;References;156
19;15 Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array;157
19.1;Abstract;157
19.2;1 Introduction;158
19.3;2 Related Work;158
19.4;3 Junction and Ambient Temperatures;159
19.5;4 Stub Series Terminated Logic;160
19.5.1;4.1 Junction Temperature with SSTL135 I/O Standard for Auto RAM Style;160
19.5.2;4.2 Junction Temperature with SSTL135I/O Standard for Distributed RAM Style;160
19.5.3;4.3 Junction Temperature with SSTL135 I/O Standard for Bufgdll BRAM;160
19.6;5 Thermal Analysis of Different RAM Styles;160
19.6.1;5.1 For frequency Range 1–10 GHz;160
19.6.2;5.2 Power Consumption for Capacitance 5 pF and Airflow = 250 Linear Feet per Minute;164
19.6.3;5.3 Power Consumption for Capacitance 50 pF and Airflow = 500 Linear Feet per Minute;165
19.6.4;5.4 Power Consumption for 1–10 GHz;166
19.7;6 Conclusion;166
19.8;7 Future Scope;167
19.9;References;167
20;16 Ardudroid Surveillance Bot;168
20.1;Abstract;168
20.2;1 Introduction;168
20.3;2 Hardware Design;169
20.3.1;2.1 Android Device;170
20.3.2;2.2 Bot Chassis;170
20.3.3;2.3 Microcontroller Board (Arduino UNO);170
20.3.4;2.4 Bluetooth Module;171
20.3.5;2.5 Motor Driver Board;172
20.3.6;2.6 DC Motor;172
20.4;3 Electronics of the System;173
20.5;4 Software Implementation;174
20.6;5 Conclusion and Significance;177
20.7;References;177
21;17 Development of Cross-Toolchain and Linux Device Driver;179
21.1;Abstract;179
21.2;1 Introduction;180
21.3;2 Cross-Toolchain;180
21.3.1;2.1 Building a Cross-Compiler Toolchain;181
21.4;3 Porting Linux on Mini2440;182
21.5;4 Working on Qt Applications;184
21.6;5 Implementation of Character Driver;186
21.7;6 Sockets;187
21.8;7 Results and Conclusion;187
21.9;References;188
22;18 Design and Implementation of a Green Traffic Light Controller on FPGA Using VHDL;190
22.1;Abstract;190
22.2;1 Introduction;190
22.3;2 Traffic Light Design;191
22.4;3 Clock Gating;192
22.5;4 XPower Analyser Results;193
22.6;5 Simulation Results;194
22.7;6 Conclusion;195
22.8;References;195
23;19 Suboptimal Controller Design for Power System Model;196
23.1;Abstract;196
23.2;1 Introduction;196
23.3;2 Aggregation Technique;197
23.4;3 Results and Discussion;198
23.5;4 Conclusion;203
23.6;References;203
24;20 Designing and Simulation of S-Shaped Dielectric Resonator Antenna with Air Gap;204
24.1;Abstract;204
24.2;1 Introduction;204
24.3;2 Overview and Antenna Configuration;205
24.4;3 Simulated Results and Parametric Discussion;206
24.5;4 Conclusions;210
24.6;5 Future Scope;210
24.7;References;211
25;21 Trajectory Generation for Driver Assistance System;212
25.1;Abstract;212
25.2;1 Introduction;213
25.3;2 Block Components and Process Implemented;214
25.3.1;2.1 Sensors;214
25.3.2;2.2 Radar;215
25.3.3;2.3 Intervehicle Communication;215
25.4;3 Algorithms;218
25.5;4 Result;218
25.6;5 Conclusion;220
25.7;6 Future Scope;220
25.8;References;220
26;22 Performance Enhancement of MRPSOC for Multimedia Applications;221
26.1;Abstract;221
26.2;1 Introduction;222
26.3;2 Proposed System;222
26.3.1;2.1 Reconfigurable Instruction Set Processor;223
26.3.2;2.2 Architecture of RFU;224
26.3.3;2.3 Methodology for MRPSOC;225
26.3.3.1;2.3.1 Profiling Step;226
26.3.3.2;2.3.2 Identifying Step;226
26.3.3.3;2.3.3 Optimization Step;226
26.3.3.4;2.3.4 Assignment Step;226
26.3.4;2.4 Algorithm for MRPSOC;226
26.3.5;2.5 Data-Level Parallelism;227
26.3.6;2.6 Instruction-Level Parallelism;227
26.3.7;2.7 Memory-Level Parallelism;228
26.4;3 Simulation Results;228
26.4.1;3.1 Simulation of MPSOC;228
26.4.2;3.2 Simulation of Integrated Processor (MRPSOC and Multigrain Parallelism);230
26.5;4 Conclusion;230
26.6;References;231
27;23 A New CPU Scheduling Algorithm Using Round-robin and Mean of the Processes;232
27.1;Abstract;232
27.2;1 Introduction;233
27.3;2 Literature Overview;234
27.3.1;2.1 Terminology;234
27.3.2;2.2 Related Works;235
27.4;3 Proposed Model;235
27.4.1;3.1 Assumptions;235
27.4.2;3.2 Algorithm;235
27.4.3;3.3 Proposed Work Flow;236
27.5;4 Illustrative Examples and Discussion;237
27.6;5 Conclusion and Future Scope;240
27.7;References;241
28;24 Synchronization of Two Chaotic Oscillators Through Threshold Coupling;242
28.1;Abstract;242
28.2;1 Introduction;242
28.3;2 Literature Overview;243
28.4;3 Modeling and Simulation of Chaotic System;244
28.4.1;3.1 Dynamic Modeling of Single System;244
28.4.2;3.2 Coupled Systems Through Threshold Controller;244
28.5;4 Simulation Result of Coupled System Through Threshold Controller Coupling;246
28.6;5 Conclusion;247
28.7;Acknowledgements;247
28.8;References;247
29;25 L3C Model of High-Performance Computing Cluster for Scientific Applications;249
29.1;Abstract;249
29.2;1 Introduction;250
29.3;2 Performance of HPCC;250
29.4;3 Scientific Applications on HPCC;251
29.5;4 Factors Governing Performance for Scientific Applications;251
29.6;5 Models for Understanding HPCC Performance for Scientific Applications;252
29.7;6 L3C Model of HPCC for Scientific Applications;256
29.8;7 Implications of L3C Model;258
29.9;8 Conclusions;259
29.10;References;260
30;26 Design and Development of Digital Energy Meter on FPGA;261
30.1;Abstract;261
30.2;1 Introduction;262
30.3;2 FPGA Architecture and Design Flow;263
30.3.1;2.1 FPGA and Its Architecture;263
30.3.2;2.2 FPGA Design Flow;264
30.4;3 Advantages of FPGA;264
30.5;4 Implementation Details;265
30.5.1;4.1 ADC Module;265
30.5.2;4.2 Zero Crossing Detector;266
30.5.3;4.3 Counter Module;266
30.5.4;4.4 Peak Detector;266
30.5.5;4.5 Float to ASCII Conversion;266
30.5.6;4.6 Communication Module;266
30.6;5 IP Cores;267
30.6.1;5.1 Floating-Point Core;267
30.6.2;5.2 CORDIC;268
30.7;6 Test Results;268
30.8;7 Conclusion;272
30.9;Acknowledgements;273
30.10;References;273
31;27 Design of a Hypothetical Processor Using Re-configurable Logic in VHDL;274
31.1;Abstract;274
31.2;1 Introduction;274
31.3;2 Design of Processor;276
31.3.1;2.1 Arithmetic, Logical, and Shift Unit;276
31.3.2;2.2 Shifter Unit;278
31.3.3;2.3 Register File;279
31.4;3 Simulation;280
31.5;4 Conclusion;282
31.6;References;282
32;28 Aspects Involved in the Modeling of PV System, Comparison of MPPT Schemes, and Study of Different Ambient Conditions Using P&O Method;283
32.1;Abstract;283
32.2;1 Introduction;283
32.3;2 Mathematical Model of Photovoltaic Cell;284
32.3.1;2.1 Photovoltaic Cell;284
32.3.2;2.2 Modeling the Photovoltaic Array;285
32.4;3 Maximum Power Point Tracking and Converters Used in PV System;289
32.4.1;3.1 Need of MPPT and Converters;289
32.4.2;3.2 MPPT Schemes and Their Comparison;289
32.4.3;3.3 DC–DC Boost Converter—Designing;292
32.5;4 Perturbation and Observation Technique;294
32.6;5 Model of Used Flowchart in Simulink;294
32.7;6 Simulation Result;296
32.8;7 Conclusion;300
32.9;References;300
33;29 A Novel Approach for Data Classification Using Neutrosophic Entropy;302
33.1;Abstract;302
33.2;1 Introduction;302
33.3;2 Dataset Details;304
33.4;3 Classification Based on Fuzzy Probability;305
33.4.1;3.1 Basic Criteria for Determining Fuzzy Probability;305
33.4.2;3.2 Basic Criteria for Determining Fuzzy Entropy;306
33.5;4 Classification Based on Neutrosophic Probability;306
33.5.1;4.1 Basic Criteria for Determining Neutrosophic Probability;307
33.5.2;4.2 Basic Criteria for Neutrosophic Entropy;308
33.6;5 Implementation of Fuzzy Probability and Neutrosophic Probability on Appendicitis Dataset;308
33.7;6 Experiments and Results;310
33.8;7 Conclusion and Future Scope;313
33.9;References;314
34;30 SDN Layer 2 Switch Simulation Using Mininet and OpenDayLight;315
34.1;Abstract;315
34.2;1 Introduction;315
34.2.1;1.1 Problem Definition;316
34.3;2 Theory;316
34.3.1;2.1 OpenFlow;316
34.3.2;2.2 OpenDaylight;318
34.3.3;2.3 Layer 2 Switch;319
34.4;3 Simulation Design;320
34.4.1;3.1 Network Design;320
34.4.2;3.2 SDN Controller;320
34.4.3;3.3 Procedure for Simulation;321
34.5;4 Result;321
34.6;5 Conclusion;322
34.7;References;323
35;31 An Architectural Design for Knowledge Asset Management System;324
35.1;Abstract;324
35.2;1 Introduction;325
35.3;2 Knowledge Asset Management Processes and Actors;327
35.4;3 Architecture of Knowledge Asset Management (KAM) System;329
35.5;4 Comparative Analysis and Advantages of the Proposed System;331
35.6;5 Conclusion;332
35.7;References;333

Über Autor(innen)

Prof. Sunil Kumar Muttoo is working as a Professor and Head of the Department of Computer Science, University of Delhi. He completed his M.Sc., M.Phil., Ph.D. at the University of Delhi and his M.Tech. (Computer Science and Data Processing, CSDP) at the Indian Institute of Technology Kharagpur (IIT-KGP). He is involved in research in the field of steganography and digital watermarking. He has published more than sixty papers in international/national journals and conference/workshop proceedings. He has more than 30 years of teaching and research experience.