Radecka / Zilic Verification by Error Modeling

Using Testing Techniques in Hardware Verification
1. Auflage 2005
ISBN: 978-0-306-48739-2
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 25, 233 Seiten

Reihe: Frontiers in Electronic Testing

Verification presents the most time-consuming task in the integrated circuit design process. The increasing similarity between implementation verification and the ever-needed task of providing vectors for manufacturing fault testing is tempting many professionals to combine verification and testing efforts.

This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. The book brings the results in the direction of merging manufacturing test vector generation and verification. It first discusses error fault models suitable for approaching the verification by testing methods. Then, it elaborates a proposal for an implicit fault model that uses the Arithmetic Transform representation of a circuit and the faults. Presented is the fundamental link between the error size and the test vector size, which allows parametrizable verification by test vectors. Furthermore, the test vector set is sufficient not only for detecting, but also for diagnosing and correcting the design errors.

The practical use of any such simulation-based verification scheme can be seriously impaired by redundant faults, that otherwise require exhaustive simulations. The redundant fault identification methods are presented that are well suited for the type of faults considered. Finally, the same representation can be used to augment and expand the formal verification schemes that are to be used in conjunction with the simulation-based verification.

The primary audience for Verification by Error Modeling includes researchers in verification and testing, managers in charge of verification of test and practicing engineers. Due to its comprehensive coverage of background topics, the book can also be used for teaching courses on verification and test topics.

Written for:
Researchers in verification and testing, managers in charge of verification of test and practicing engineers

Autoren/Hrsg.

Radecka, Katarzyna

Zilic, Zeljko

Inhaltsverzeichnis

1;Contents;7
2;List of Figures;11
3;Acknowledgments;15
4;Chapter 1 INTRODUCTION;16
4.1;1. DESIGN FLOW;16
4.2;2. VERIFICATION – APPROACHES AND PROBLEMS;19
4.2.1;2.1 Verification Approaches;20
4.2.2;2.2 Verification by Simulations;20
4.2.3;2.3 Test Vector Generation;20
4.2.4;2.4 Design Error Models;22
4.2.5;2.5 Other Simulation Methods;24
4.2.6;2.6 Formal Verification;26
4.2.7;2.7 Model- based Formal Verification Methods;27
4.2.8;2.8 Proof- theoretical Formal Verification Methods;29
4.2.9;2.9 Spectral Methods in Verification;29
4.3;3. BOOK OBJECTIVES;30
5;Chapter 2 BOOLEAN FUNCTION REPRESENTATIONS;34
5.1;1. BACKGROUND - FUNCTION REPRESENTATIONS;34
5.1.1;1.1 Truth Tables;35
5.1.2;1.2 Boolean Equations - Sum of Products;36
5.1.3;1.3 Satisfiability of Boolean Functions;38
5.1.4;1.4 Shannon Expansion;43
5.1.5;1.5 Polynomial Representation;43
5.2;2. DECISION DIAGRAMS;45
5.2.1;2.1 Reduced Ordered Binary Decision Diagrams;46
5.2.2;2.2 Word- Level Decision Diagrams;48
5.3;3. SPECTRAL REPRESENTATIONS;53
5.3.1;3.1 Walsh- Hadamard Transform;54
5.3.2;3.2 Walsh Transform Variations;55
5.3.3;3.3 Walsh-Hadamard Transform as Fourier Transform;56
5.4;4. ARITHMETIC TRANSFORM;59
5.4.1;4.1 Calculation of Arithmetic Transform;62
5.4.2;4.2 AT and Word- Level Decision Diagrams;64
6;Chapter 3 DON’T CARES AND THEIR CALCULATION;66
6.1;1. INCOMPLETELY SPECIFIED BOOLEAN FUNCTIONS;66
6.1.1;1.1 Don’t Cares in Logic Synthesis;66
6.1.2;1.2 Don’t Cares in Testing for Manufacturing Faults;67
6.1.3;1.3 Don’t Cares in Circuit Verification;69
6.2;2. USING DON’T CARES FOR REDUNDANCY IDENTIFICATION;70
6.2.1;2.1 Basic Definitions;71
6.2.2;2.2 Calculation of All Don’t Care Conditions;72
6.2.3;2.3 Algorithms for Computing ODCs;80
6.2.4;2.4 Approximations to Observability Don’t Cares - CODCs;82
7;Chapter 4 TESTING;86
7.1;1. INTRODUCTION;86
7.2;2. FAULT LIST REDUCTION;88
7.3;3. OVERVIEW OF SIMULATORS;88
7.3.1;3.1 True- Value Simulator Types;89
7.3.2;3.2 Logic Simulators;90
7.4;4. FAULT SIMULATORS;94
7.4.1;4.1 Random Simulations;96
7.5;5. DETERMINISTIC VECTOR GENERATION – ATPG;109
7.5.1;5.1 Deterministic Phase;109
7.5.2;5.2 Search for Vectors;113
7.5.3;5.3 Fault Diagnosis;115
7.6;6. CONCLUSIONS;116
8;Chapter 5 DESIGN ERROR MODELS;118
8.1;1. INTRODUCTION;118
8.2;2. DESIGN ERRORS;120
8.3;3. EXPLICIT DESIGN ERROR MODELS;122
8.3.1;3.1 Detecting Explicit Errors;125
8.4;4. IMPLICIT ERROR MODEL PRECURSORS;127
8.4.1;4.1 Rationale for Implicit Models;128
8.4.2;4.2 Related Work – Error Models;129
8.5;5. ADDITIVE IMPLICIT ERROR MODEL;130
8.5.1;5.1 Arithmetic Transform of Basic Design Errors;132
8.6;6. DESIGN ERROR DETECTION AND CORRECTION;138
8.6.1;6.1 Path Trace Procedure;140
8.6.2;6.2 Back- propagation;141
8.6.3;6.3 Boolean Difference Approximation by Simulations;142
8.7;7. CONCLUSIONS;143
9;Chapter 6 DESIGN VERIFICATION BY AT;144
9.1;1. INTRODUCTION;144
9.2;2. DETECTING SMALL AT ERRORS;147
9.2.1;2.1 Universal Test Set;147
9.2.2;2.2 AT- based Universal Diagnosis Set;148
9.3;3. BOUNDING ERROR BY WALSH TRANSFORM;150
9.3.1;3.1 Spectrum Comparison;152
9.3.2;3.2 Spectrum Distribution and Partial Spectra Comparison;153
9.3.3;3.3 Absolute Value Comparison;155
9.4;4. EXPERIMENTAL RESULTS;157
9.5;5. CONCLUSIONS;161
10;Chapter 7 IDENTIFYING REDUNDANT GATE AND WIRE REPLACEMENTS;162
10.1;1. INTRODUCTION;162
10.2;2. GATE REPLACEMENT FAULTS;164
10.2.1;2.1 Redundant Replacement Faults;165
10.3;3. REDUNDANCY DETECTION BY DON’T CARES;166
10.3.1;3.1 Using Local Don’t Cares;167
10.3.2;3.2 Using Testing - Single Minterm Approximation;169
10.3.3;3.3 Redundant Single Cube Replacements;174
10.4;4. EXACT REDUNDANT FAULT IDENTIFICATION;178
10.5;5. IDENTIFYING REDUNDANT WIRE REPLACEMENTS;179
10.5.1;5.1 Wire Replacement Faults and Rewiring;181
10.5.2;5.2 Detection by Don’t Cares;182
10.5.3;5.3 Don’t Care Approximations;184
10.5.4;5.4 SAT for Redundant Wire Identification;185
10.6;6. EXACT WIRE REDUNDANCY IDENTIFICATION;187
10.7;7. I/O PORT REPLACEMENT DETECTION;190
10.7.1;7.1 Detection of I/ O Port Wire Switching Errors;190
10.8;8. EXPERIMENTAL RESULTS;192
10.8.1;8.1 Gate Replacement Experiments;192
10.8.2;8.2 Wire Replacement Experiments;197
10.8.3;8.3 SAT vs. ATPG;200
10.9;9. CONCLUSIONS;200
11;Chapter 8 CONCLUSIONS AND FUTURE WORK;202
11.1;1. CONCLUSIONS;202
11.2;2. FUTURE WORK;204
12;Appendicies;206
13;References;212
14;Index;226