Formal Verification

An Essential Toolkit for Modern VLSI Design
2. Auflage 2023
ISBN: 978-0-323-95612-3
Verlag: Elsevier Science & Technology

Buch, Englisch, 424 Seiten, Format (B × H): 235 mm x 190 mm, Gewicht: 882 g

Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes.

Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity.

Autoren/Hrsg.

Seligman, Erik

Schubert, Tom

Kumar, M V Achutha Kiran

Fachgebiete

• Mathematik | Informatik EDV | Informatik Informatik Logik, formale Sprachen, Automaten
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf

Inhaltsverzeichnis

- Formal verification: from dreams to reality
- Basic formal verification algorithms
- Introduction to SystemVerilog Assertions
- Formal property verification
- Effective formal property verification for design exercise
- Effective FPV for verification
- Formal property verification apps for specific problems
- Formal equivalence verification
- Formal verification's greatest bloopers: the danger of false positives
- Dealing with complexity
- Formal signoff on real projects
- Your new FV-aware lifestyle

Über Autor(innen)

Schubert, Tom
Tom Schubert is on the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis.

Kumar, M V Achutha Kiran
M V Achutha Kiran Kumar is an Intel Fellow in the Design Engineering group at intel and leads the company's Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 19 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of validation including formal verification. He is the co-author of 'Formal Verification - An Essential toolkit for the Hardware Design'.