Computer Organization, Design, and Architecture

6. Auflage 2025
ISBN: 978-1-032-80512-2
Verlag: CRC Press

Buch, Englisch, 807 Seiten, Format (B × H): 183 mm x 260 mm, Gewicht: 1685 g

This unique and classroom-proven text provides a hands-on introduction to the design of computer systems. It depicts, step by step, the design and programming of a simple but complete hypothetical computer, followed by detailed architectural features of existing computer systems as enhancements to the structure of the simple computer. This treatment integrates the four categories of digital systems architecture: logic design, computer organization, computer hardware, and computer system architecture.

This edition incorporates updates to reflect contemporary organizations and devices, including graphics processing units (GPUs), quantum computing, and the latest supercomputer systems. It also includes a description of the two popular Instruction Set Architectures (ARM and RISC-V).

The book is suitable for a one-or two-semester undergraduate or beginning graduate course in computer science and computer engineering; its previous editions have been adopted by 120+ universities around the world.

The book covers the topics suggested by the recent IEEE/ACM curriculum for “computer architecture and organization.”

Zielgruppe

General and Postgraduate

Autoren/Hrsg.

Shiva, Sajjan G.

Fachgebiete

• Mathematik | Informatik EDV | Informatik Technische Informatik
• Mathematik | Informatik EDV | Informatik EDV & Informatik Allgemein

Inhaltsverzeichnis

1. Introduction. 2. Number Systems and Codes. 3. Combinational Logic. 4. Sequential Logic. 5. A Simple Computer: Organization and Programming. 6. A Simple Computer: Hardware Design. 7. Input/Output. 8. Processor and Instruction-Set Architectures. 9. Memory and Storage. 10. Arithmetic/Logic Unit Enhancement. 11. Control Unit Enhancement. 12. Advanced Architectures. 13. Embedded Systems. 14. Mobile Processors and Systems on Chip. 15. Computer Networks and Distributed Processing. 16. Performance Evaluation Appendix A: Details of Representative Integrated Circuit. Appendix B: Stack Implementation. Appendix C: ARM Instruction Set Architecture. Appendix D; RISC-V Instruction Set Architecture.

Über Autor(innen)

Dr. Sajjan G. Shiva is First Horizon Foundation Distinguished Professor of Computer Science at the University of Memphis. He joined the university in 2002 as the director of the Computer Science Division, transitioned it into the Department of Computer Science in 2005, and served as the founding chair through 2015. He has served on the computer science faculties at the University of Alabama in Huntsville and Alabama A&M University. He has also served as the manager of Software Quality Assurance at Teledyne Brown Engineering; senior software engineer and executive manager (Technical) at Intergraph Corporation; and technical advisor, Computer Technologies Division, U.S. Army Space and Strategic Defense Command. Dr. Shiva has consulted with industry and government organizations in the areas of software engineering, computer architecture, and artificial intelligence. He is a life fellow of IEEE and a life member of ACM. He has received research funding from NSF, NASA, U.S. Department of Defense, and ONR. His current interests are game theoretic cybersecurity, secure software engineering, and artificial intelligent systems development methodologies.