Takeda / Yang / Miura-Hamada Hot-Carrier Effects in MOS Devices

1. Auflage 1995
ISBN: 978-0-08-092622-3
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: 6 - ePub Watermark

E-Book, Englisch, 312 Seiten

The exploding number of uses for ultrafast, ultrasmall integrated circuits has increased the importance of hot-carrier effects in manufacturing as well as for other technological applications. They are rapidly movingout of the research lab and into the real world. This book is derived from Dr. Takedas book in Japanese, Hot-Carrier Effects, (published in 1987 by Nikkei Business Publishers). However, the new book is much more than a translation. Takedas original work was a starting point for developing this much more complete and fundamental text on this increasingly important topic. The new work encompasses not only all the latest research and discoveries made in the fast-paced area of hot carriers, but also includes the basics of MOS devices, and the practical considerations related to hot carriers. - Chapter one itself is a comprehensive review of MOS device physics which allows a reader with little background in MOS devices to pick up a sufficient amount of information to be able to follow the rest of the book - The book is written to allow the reader to learn about MOS Device Reliability in a relatively short amount of time, making the texts detailed treatment of hot-carrier effects especially useful and instructive to both researchers and others with varyingamounts of experience in the field - The logical organization of the book begins by discussing known principles, then progresses to empirical information and, finally, to practical solutions - Provides the most complete review of device degradation mechanisms as well as drain engineering methods - Contains the most extensive reference list on the subject

Zielgruppe

Adult: General. Academic/professional/technical: Undergraduate

Autoren/Hrsg.

Takeda, Eiji

Yang, Cary Y.

Miura-Hamada, Akemi

Inhaltsverzeichnis

1;Front Cover;1
2;Hot-Carrier Effects in MOS Devices;4
3;Copyright Page;5
4;Table of Contents;6
5;Preface;12
6;Chapter 1. MOS Device Fundamentals;14
6.1;1.1 From Discrete to ULSI;14
6.2;1.2 Physics of the MOS Diode;15
6.3;1.3 Principles of the MOSFET;36
6.4;1.4 Survey of Device and Circuit Reliability Issues Related to Hot-Carrier Effects;53
6.5;1.5 Summary;55
7;Chapter 2. Hot-Carrier Injection Mechanisms;56
7.1;2.1 Introduction;56
7.2;2.2 Avalanche Breakdown;57
7.3;2.3 Hot-Carrier Injection Mechanisms and Gate Currents;62
7.4;2.4 Gate Current Modeling;71
7.5;2.5 Summary;78
8;Chapter 3. Hot-Carrier Device Degradation;79
8.1;3.1 Introduction;79
8.2;3.2 Device Degradation Due to Various Hot-Carrier Injections;80
8.3;3.3 Modeling of Device Degradation;93
8.4;3.4 Summary;103
9;Chapter 4. AC and Process-Induced Hot-Carrier Effects;104
9.1;4.1 Introduction;104
9.2;4.2 Dynamic (AC) Stress Effects;104
9.3;4.3 Process Effects on Hot-Carrier Degradation;119
9.4;4.4 Materials Effects on Hot-Carrier Degradation;123
9.5;4.5 Summary;134
10;Chapter 5. Hot-Carrier Effects at Low Temperature and Low Voltage;135
10.1;5.1 Introduction;135
10.2;5.2 Hot-Carrier Effects at Low Temperature;136
10.3;5.3 Device Performance Degradation;136
10.4;5.4 Device Degradation Mechanisms;143
10.5;5.5 Summary;146
11;Chapter 6. Dependence of Hot-Carrier Phenomena on Device Structure;147
11.1;6.1 Introduction;147
11.2;6.2 Variations of Device Structure;148
11.3;6.3 Device Parameter Dependence;148
11.4;6.4 Device Structure Dependence;153
11.5;6.5 Summary;158
12;Chapter 7. As–P Double Diffused Drain (DDD) Versus Lightly Doped Drain (LDD) Devices;160
12.1;7.1 Introduction;160
12.2;7.2 DDD Structure and Its Fabrication Process;162
12.3;7.3 DDD Device Characteristics;163
12.4;7.4 DDD and LDD Device Operation Principles;172
12.5;7.5 LDD Device Characteristics;174
12.6;7.6 Improved LDD Devices;178
12.7;7.7 Gaussian vs Abrupt Junctions;179
12.8;7.8 Summary;185
13;Chapter 8. Gate-to-Drain Overlapped Devices (Gold);188
13.1;8.1 Introduction;188
13.2;8.2 GOLD Structure and Its Fabrication Process;189
13.3;8.3 Device Characteristics;190
13.4;8.4 Reduced Hot-Carrier Degradation;196
13.5;8.5 Summary;197
13.6;References;200
14;Index;316

Leseproben

Chapter 2 Hot-Carrier Injection Mechanisms
2.1 Introduction
In recent years, since advanced fine-line patterning technologies have made it possible for device miniaturization to approach its physical limits, interest in hot-electron injection and associated device degradation has increased. This is because hot-electron effects impose more severe constraints on very large-scale integration (VLSI) device design as device dimensions are reduced. Main interest has focused on channel hot-electron (CHE) injection. Substrate hot-electron (SHE) injection has also been used to investigate gate insulator qualities. Both of these injection mechanisms are schematically illustrated in Figure 2.1. Ning et al. [1977b] have demonstrated CHE effects extensively, since it is relatively easy to measure the injection gate current (IG) with a 2- or 3-µm Leff metal-oxide-semiconductor field-effect transistor (MOSFET). Figure 2.1 Schematic diagram of channel hot-electron (CHE) injection and substrate hot-electron (SHE) injection. However, when accounting for the causes of VLSI circuit degradation, it seems to be necessary for not only CHE but also other injection mechanisms to exist. For example, Fair and Sun [1981] have proposed a hot hole–induced degradation mechanism. In this chapter, not only the above two injections but also two newer hot-carrier injection mechanisms are discussed, both experimentally and theoretically. They are drain avalanche hot-carrier (DAHC) injection and secondarily generated hot-electron (SGHE) injection. Device degradation due to these injections is also clarified by comparing each with that due to CHE injection. Before moving on to hot-carrier injection mechanisms, the physics of hot carriers will be discussed briefly in the next section. 2.2 Avalanche Breakdown
Hot-carrier effects in Si VLSI circuits represent phenomena that are brought about by high-energy carriers created by the channel electric field. These fundamental physical mechanisms share some common characteristics with time-dependent dielectric breakdown (TDDB), radiation damage (RD) due to cosmic and a-rays, and electrostatic discharge (ESD), as shown schematically in Figure 2.2. The commonality lies in the phenomenon of avalanche multiplication. As a background on hot-carrier injection, the avalanche breakdown phenomenon is discussed below. Figure 2.2 Problems related to hot-carrier effects. 2.2.1 AVALANCHE MULTIPLICATION
The breakdown phenomenon determines the highest applicable voltage and limits the speed and power-handling capacity of discrete MOSFET devices or MOS integrated circuits. Therefore, breakdown voltage is as important as transconductance or threshold voltage in MOS device design. However, there have been few theories which account for the source–drain breakdown voltages of MOSFETs [Grove, 1967] due to the inability to estimate accurately the electric field distribution. The avalanche breakdown characteristics in MOSFETs are divided into two types. One is normal breakdown observed in p-MOSFETs or long-channel n-MOSFETs. The breakdown voltage, BVDS, decreases with an increase in gate voltage in normal breakdown. The other is negative-resistance breakdown, which is often observed in short-channel n-MOSFETs. The breakdown voltage of p-MOSFETs or long-channel n-MOSFETs increases with increase in gate voltage magnitude, as depicted in Figure 2.3a. However, BVDS decreases with increase in VG, and the sustain voltage, BV'DS apparently exists in the negative-resistance breakdown observed in short-channel n-MOSFETs as depicted in Figure 2.3b. Figure 2.3 Typical source-drain breakdown characteristics. (a) Normal breakdown in a n-channel MOSFET. (b) Negative-resistance breakdown in an p-channel MOSFET. (Reprinted with permission from T. Toyabe, K. Yamaguchi, S. Asai, and M. S. Mock, “A Numerical Model of Avalanche Breakdown in MOSFETs,” IEEE Trans. Electron Dev. 25, 825–832 (© 1978 IEEE).) These avalanche breakdown characteristics are caused by the impact ionization of carriers in the high-field region, which develops around the reverse-biased drain-substrate junction. The avalanche breakdown in a planar p–n junction can be analyzed relative easily, since the electric field is known from an analytical solution of Poisson’s equation [Sze, 1969]. The electric field distribution in the drain region of a MOSFET is more complicated because the field is intensified by the presence of the insulated gate. The two-dimensional analysis reported by Toyabe et al. [1978] shows that carrier leaves the surface at the so-called pinch-off point and flows deep within the substrate before reaching the source, as depicted in Figure 2.4. The electric field is highest just beneath the surface. However, the seed current of avalanche multiplication in this region is the small reverse-biased saturation current, ID0. In addition, the primary channel current, which is the source current, IS, is multiplied by a relatively high electric field. Thus the drain current, ID, can be written by D=M*IS+MID0.   (2.1) Figure 2.4 Cross section of an n-MOSFET showing the current components resulting from avalanche multiplication near the drain. (Reprinted with permission from T. Toyabe, K. Yamaguchi, S. Asai, and M. S. Mock, “A Numerical Model of Avalanche Breakdown in MOSFETs,” IEEE Trans. Electron Dev. 25, 825–832 (© 1978 IEEE).) The multiplication factors, M and M*, are given by =1/1-Iion   (2.2) and *=1/1-Iion*,   (2.3) where Iion and I*ion are ionization integrals. Iion is obtained as ion=?anexp-?xan-apdx'dx,   (2.4) where an and ap are the ionization rates of electrons and holes, respectively. The integration path is along the channel (in the x-direction). Similarly, I*ion is expressed as ion*=?anexp-??an-apd?'d?,   (2.5) where the integration is carried out along the channel current path represented by a curvilinear coordinate ?. The channel current path is determined by locating the position of the maximum current density on each vertical grid line and connecting these positions. an and ap are calculated as functions of the electric field using the expression given by Niehaus et al. [1973]. 2.2.2 NORMAL BREAKDOWN
The normal breakdown as depicted in Figure 2.3a shows a current–voltage behavior similar to breakdown characteristics of a reverse-biased p–n junction. The second term on the right-hand side of Eq. (2.1) is responsible for this breakdown. The device is then expected to have normal breakdown when the multiplication factor M becomes infinity. Thus the normal breakdown voltage is the drain voltage which makes the ionization integral, Iion, equal to unity. 2.2.3 NEGATIVE-RESISTANCE BREAKDOWN
The negative-resistance breakdown observed in short-channel n-MOSFETs occurs at a voltage lower than those expected from the normal breakdown voltages of long-channel devices. Therefore, a rapid increase in drain current at breakdown is expected to come from the multiplication of the source current, which is represented by the first term on the right side of Equation (2.1). The excess substrate current, ISUB, is obtained from Eq. (2.1) as SUB=ID-IS?M*-1IS,   (2.6) where the term MID0 in Eq. (2.1) is ignored, since M is on the order of unity and ID0 is much smaller than IS. A voltage drop of RsubISUB across the substrate resistance acts as a back bias in the forward direction. This positive back-biasing increases the source current, Is, and, subsequently, ISUB. This increase continues until the substrate–source junction is turned on. Then, a smaller voltage is sufficient to sustain a higher current, resulting in negative resistance. The potential at the lower boundary of the intrinsic FET is assumed to be constant as shown in Figure 2.4. Thus the back bias (substrate-to-source voltage), VSUB, is given as SUB=-ISUBRsub+VSUB0,   (2.7) where VSUB0 is the external back-bias voltage. From Eqs. (2.6) and...