Devices, Circuits and Systems
Buch, Englisch, 368 Seiten, Format (B × H): 170 mm x 251 mm, Gewicht: 712 g
ISBN: 978-1-118-51188-6
Verlag: Wiley
Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics. This bookteaches the fundamentals of electrical overstress and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design. It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in specific technologies, circuits, and chips. The book is unique in covering the EOS manufacturing issues from on-chip design and electronic design automation to factory-level EOS program management in today's modern world.
Look inside for extensive coverage on:
* Fundamentals of electrical overstress, from EOS physics, EOS time scales, safe operating area (SOA), to physical models for EOS phenomena
* EOS sources in today's semiconductor manufacturing environment, and EOS program management, handling and EOS auditing processing to avoid EOS failures
* EOS failures in both semiconductor devices, circuits and system
* Discussion of how to distinguish between EOS events, and electrostatic discharge (ESD) events (e.g. such as human body model (HBM), charged device model (CDM), cable discharge events (CDM), charged board events (CBE), to system level IEC 61000-4-2 test events)
* EOS protection on-chip design practices and how they differ from ESD protection networks and solutions
* Discussion of EOS system level concerns in printed circuit boards (PCB), and manufacturing equipment
* Examples of EOS issues in state-of-the-art digital, analog and power technologies including CMOS, LDMOS, and BCD
* EOS design rule checking (DRC), LVS, and ERC electronic design automation (EDA) and how it is distinct from ESD EDA systems
* EOS testing and qualification techniques, and
* Practical off-chip ESD protection and system level solutions to provide more robust systems
Electrical Overstress (EOS): Devices, Circuits and Systems is a continuation of the author's series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the nano-electronic era.
Autoren/Hrsg.
Fachgebiete
Weitere Infos & Material
About the Author xvii
Preface xix
Acknowledgements xxiii
1 Fundamentals of Electrical Overstress 1
1.1 Electrical Overstress 2
1.2 De-Mystifying Electrical Overstress 7
1.3 Sources of Electrical Overstress 8
1.4 Misconceptions of Electrical Overstress 10
1.5 Minimization of Electrical Overstress Sources 11
1.6 Mitigation of Electrical Overstress 11
1.7 Signs of Electrical Overstress Damage 12
1.8 Electrical Overstress and Electrostatic Discharge 14
1.9 Electromagnetic Interference 20
1.10 Electromagnetic Compatibility 21
1.11 Thermal Over-Stress 21
1.12 Reliability Technology Scaling 23
1.13 Safe Operating Area 26
1.14 Summary and Closing Comments 28
References 29
2 Fundamentals of EOS Models 36
2.1 Thermal Time Constants 36
2.2 Pulse Event Time Constants 39
2.3 Mathematical Methods for EOS 42
2.4 The Spherical Model - Tasca Derivation 57
2.5 The One-dimensional Model - Wunsch-Bell Derivation 62
2.6 The Ash Model 68
2.7 The Cylindrical Model - The Arkihpov-Astvatsaturyan-Godovosyn-Rudenko Derivation 68
2.8 The Three-dimensional Parallelepiped Model - Dwyer-Franklin-Campbell Derivation 69
2.9 The Resistor Model - Smith-Littau Derivation 76
2.10 Instability 79
2.11 Electro-migration and Electrical Overstress 84
2.12 Summary and Closing Comments 84
References 85
3 EOS, ESD, EMI, EMC and Latchup 87
3.1 Electrical Overstress Sources 87
3.2 EOS Failure Mechanisms 94
3.3 Failure Mechanism - Latchup or EOS? 97
3.4 Failure Mechanism - Charged Board Model or EOS? 98
3.5 Summary and Closing Comments 99
References 99
4 EOS Failure Analysis 102
4.1 Electrical Overstress Failure Analysis 102
4.2 EOS Failure Analysis - Choosing the Correct Tool 112
4.3 Summary and Closing Comments 129
References 130
5 EOS Testing and Simulation 133
5.1 Electrostatic Discharge Testing - Component Level 133
5.2 Transmission Line Pulse Testing 140
5.3 ESD Testing - System Level 143
5.4 Electrical Overstress Testing 148
5.5 EOS Testing - Lightning 149
5.6 EOS Testing - IEC 61000-4-5 150
5.7 EOS Testing - Transmission Line Pulse Method and EOS 151
5.8 EOS Testing - D.C. and Transient Latchup 153
5.9 EOS Testing - Scanning Methodologies 154
5.10 Summary and Closing Comments 161
References 161
6 EOS Robustness - Semiconductor Technologies 166
6.1 EOS and CMOS Technology 166
6.2 EOS and RF CMOS and Bipolar Technology 180
6.3 EOS and LDMOS Power Technology 186
6.4 Summary and Closing Comments 194
References 195
7 EOS Design - Chip Level Design and Floor Planning 196
7.1 EOS and ESD Co-Synthesis - How to Design for Both EOS and ESD 196
7.2 Product Definition Flow and Technology Evaluation 197
7.3 EOS Product Definition Flow - Constant Reliability Scaling 199
7.4 EOS Product Definition Flow - Bottom Up Design 200
7.5 EOS Product Definition Flow - Top Down Design 200
7.6 On-Chip EOS Considerations - Bond Pad and Bond Wire Design 202
7.7 EOS Peripheral I/O Floor Planning 202
7.8 EOS Chip Power Grid Design - IEC Specification Power Grid and Interconnect Design Considerations 206
7.9 Printed Circuit Board Design 209
7.10 Summary and Closing Comments 211
References 211
8 EOS Design - Chip Level Circuit Design 213
8.1 EOS Protection Devices 213
8.2 EOS Protection Device Classification Characteristics 213
8.3 EOS Protection Device - Directionality 216
8.4 EOS Protection Device Classification - I-V Characteristic Type 217
8.5 EOS Protection Device Design Window 220
8.6 EOS Protection Device - Types of Voltage Suppression Devices 222
8.7 EOS Protection Device - Types of Current-Limiting Devices 229
8.8 EOS Protection - Across Board Supply and Ground Plane Using a Transient Voltage Suppression Device and Schottky Diodes 236
8.9 EOS and ESD Protection Co-Synthesis Network 237
8.10 Co-Synthesis of EOS in Cables and PCBs 237
8.11 Summary and Closing Comments 239
References 239
9 EOS Prevention and Control 240
9.1 Controlling EOS 240
9.2 EOS Minimization 242
9.3 EOS Minimization - Preventive Actions in the Design Process 246
9.4 EOS Prevention - EOS Guidelines and Procedures 246
9.5 EOS Prevention - Ground Testing 247
9.6 EOS Prevention - Connectivity 247
9.7 EOS Prevention - Insertion 247
9.8 EOS and Electromagnetic Interference Prevention - Printed Circuit Board Design 248
9.9 EOS Prevention - Desktop Boards 251
9.10 EOS Prevention - On-Board and On-Chip Design Solutions 252
9.11 High Performance Serial Buses and EOS 257
9.12 Summary and Closing Comments 259
References 259
10 EOS Design - Electronic Design Automation 263
10.1 EOS and Electronic Design Automation 263
10.2 EOS and ESD Design Rule Checking 263
10.3 EOS Electronic Design Automation 266
10.4 Printed Circuit Board Design Checking and Verification 270
10.5 EOS and Latchup Design Rule Checking 273
10.6 Summary and Closing Comments 282
References 282
11 EOS Program Management 285
11.1 EOS Audits and Manufacturing Control 285
11.2 Controlling EOS in the Production Process 287
11.3 EOS and Assembly Plant Corrective Actions 287
11.4 EOS Audits - From Manufacturing to Assembly Control 288
11.5 EOS Program - Weekly, Monthly, Quarterly, to Annual Audits 288
11.6 EOS and ESD Design Release 289
11.7 EOS Design, Testing and Qualification 297
11.8 Summary and Closing Comments 298
References 298
12 Electrical Overstress in Future Technologies 301
12.1 EOS Future Implications for Future Technologies 301
12.2 EOS in Advanced CMOS Technology 302
12.3 EOS Implications in 2.5-D and 3-D Systems 304
12.4 EOS and Magnetic Recording 309
12.5 EOS and Micro-Machines 312
12.6 EOS and RF MEMs 316
12.7 EOS Implications for Nano-Structures 318
12.8 Summary and Closing Comments 322
References 322
Appendix A: Glossary of Terms 329
Appendix B: Standards 335
Index 339
