From Components to Systems
Buch, Englisch, 336 Seiten, Format (B × H): 178 mm x 251 mm, Gewicht: 629 g
ISBN: 978-0-470-51191-6
Verlag: Wiley
With the evolution of semiconductor technology and global diversification of the semiconductor business, testing of semiconductor devices to systems for electrostatic discharge (ESD) and electrical overstress (EOS) has increased in importance.
ESD Testing: From Components to Systems updates the reader in the new tests, test models, and techniques in the characterization of semiconductor components for ESD, EOS, and latchup.
Key features:
- Provides understanding and knowledge of ESD models and specifications including human body model (HBM), machine model (MM), charged device model (CDM), charged board model (CBM), cable discharge events (CDE), human metal model (HMM), IEC 61000-4-2 and IEC 61000-4-5.
- Discusses new testing methodologies such as transmission line pulse (TLP), to very fast transmission line pulse (VF-TLP), and future methods of long pulse TLP, to ultra-fast TLP (UF-TLP).
- Describes both conventional testing and new testing techniques for both chip and system level evaluation.
- Addresses EOS testing, electromagnetic compatibility (EMC) scanning, to current reconstruction methods.
- Discusses latchup characterization and testing methodologies for evaluation of semiconductor technology to product testing.
ESD Testing: From Components to Systems is part of the authors’ series of books on electrostatic discharge (ESD) protection; this book will be an invaluable reference for the professional semiconductor chip and system-level ESD and EOS test engineer. Semiconductor device and process development, circuit designers, quality, reliability and failure analysis engineers will also find it an essential reference. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, semiconductor testing and experimental work.
Autoren/Hrsg.
Fachgebiete
Weitere Infos & Material
About the Author xvii
Preface xix
Acknowledgments xxiii
1 Introduction 1
1.1 Testing for ESD, EMI, EOS, EMC, and Latchup 1
1.2 Component and System Level Testing 1
1.3 Qualification Testing 2
1.4 ESD Standards 3
1.4.1 Standard Development – Standard Practice (SP) and Standard Test Methods (STMs) 3
1.4.2 Repeatability 4
1.4.3 Reproducibility 4
1.4.4 Round Robin Testing 4
1.4.5 Round Robin Statistical Analysis – k-Statistics 5
1.4.6 Round Robin Statistical Analysis – h-Statistics 6
1.5 Component Level Standards 6
1.6 System Level Standards 7
1.7 Factory and Material Standards 7
1.8 Characterization Testing 8
1.8.1 Semiconductor Component Level Characterization 9
1.8.2 Semiconductor Device Level Characterization 9
1.8.3 Wafer Level ESD Characterization Testing 9
1.8.4 Device Characterization Tests on Circuits 10
1.8.5 Device Characterization Tests on Components 10
1.8.6 System level Characterization on Components 11
1.8.7 Testing to Standard Specification Levels 11
1.8.8 Testing to Failure 11
1.9 ESD Library Characterization and Qualification 12
1.10 ESD Component Standards and Chip Architectures 12
1.10.1 Relationship Between ESD Standard Pin Combinations and Failure Mechanisms 12
1.10.2 Relationship Between ESD Standard Pin Combinations and Chip Architecture 13
1.11 System Level Characterization 13
1.12 Summary and Closing Comments 13
Problems 14
References 15
2 Human Body Model 17
2.1 History 17
2.2 Scope 18
2.3 Purpose 18
2.4 Pulse Waveform 18
2.5 Equivalent Circuit 19
2.6 Test Equipment 20
2.7 Test Sequence and Procedure 23
2.8 Failure Mechanisms 25
2.9 HBM ESD Current Paths 26
2.10 HBM ESD Protection Circuit Solutions 28
2.11 Alternate Test Methods 32
2.11.1 HBM Split Fixture Testing 32
2.11.2 HBM Sample Testing 33
2.11.3 HBM Wafer Level ESD Testing 33
2.11.4 HBM Test Extraction Across the Device Under Test (DUT) 33
2.12 HBM Two-Pin Stress 34
2.12.1 HBM Two-Pin Stress – Advantages 37
2.12.2 HBM Two-Pin Stress – Pin Combinations 37
2.13 HBM Small Step Stress 37
2.13.1 HBM Small Step Stress – Advantages 38
2.13.2 HBM Small Step Stress – Data Analysis Methods 38
2.13.3 HBM Small Step Stress – Design Optimization 38
2.14 Summary and Closing Comments 38
Problems 39
References 39
3 Machine Model 43
3.1 History 43
3.2 Scope 43
3.3 Purpose 43
3.4 Pulse Waveform 44
3.4.1 Comparison of Machine Model (MM) and Human Body Model (HBM) Pulse Waveform 44
3.5 Equivalent Circuit 45
3.6 Test Equipment 45
3.7 Test Sequence and Procedure 47
3.8 Failure Mechanisms 49
3.9 mm ESD Current Paths 49
3.10 mm ESD Protection Circuit Solutions 52
3.11 Alternate Test Methods 55
3.11.1 Small Charge Model (SCM) 55
3.12 Machine Model to Human Body Model Ratio 57
3.13 Machine Model Status as an ESD Standard 58
3.14 Summary and Closing Comments 58
Problems 59
References 59
4 Charged Device Model (CDM) 61
4.1 History 61
4.2 Scope 61
4.3 Purpose 62
4.4 Pulse Waveform 62
4.4.1 Charged Device Model Pulse Waveform 62
4.4.2 Comparison of Charged Device Model (CDM) and Human Body Model (HBM) Pulse Waveform 63
4.5 Equivalent Circuit 65
4.6 Test Equipment 65
4.7 Test Sequence and Procedure 67
4.8 Failure Mechanisms 69
4.9 CDM ESD Current Paths 70
4.10 CDM ESD Protection Circuit Solutions 72
4.11 Alternative Test Methods 74
4.11.1 Alternative Test Methods – Socketed Device Model (SDM) 74
4.12 Charged Board Model (CBM) 75
4.12.1 Comparison of Charged Board Model (CBM) and Charged Device Model (CDM) Pulse Waveform 75
4.12.2 Charged Board Model (CBM) as an ESD Standard 77
4.13 Summary and Closing Comments 77
Problems 79
References 80
5 Transmission Line Pulse (TLP) Testing 84
5.1 History 84
5.2 Scope 85
5.3 Purpose 85
5.4 Pulse Waveform 86
5.5 Equivalent Circuit 87
5.6 Test Equipment 88
5.6.1 Current Source 90
5.6.2 Time Domain Reflection (TDR) 90
5.6.3 Time Domain Transmission (TDT) 91
5.6.4 Time Domain Reflection and Transmission (TDRT) 91
5.6.5 Commercial Transmission Line Pulse (TLP) Systems 92
5.7 Test Sequence and Procedure 95
5.7.1 TLP Pulse Analysis 96
5.7.2 Measurement Window 96
5.7.3 Measurement Analysis – TDR Voltage Waveform 96
5.7.4 Measurement Analysis – Time Domain Reflection (TDR) Current Waveform 97
5.7.5 Measurement Analysis – Time Domain Reflection (TDR) Current–Voltage Characteristic 98
5.8 TLP Pulsed I–V Characteristic 98
5.8.1 TLP I–V Characteristic Key Parameters 99
5.8.2 TLP Power Versus Time 99
5.8.3 TLP Power Versus Time – Measurement Analysis 100
5.8.4 TLP Power-to-Failure Versus Pulse Width Plot 100
5.9 Alternate Methods 101
5.9.1 Long Duration TLP (LD-TLP) 101
5.9.2 Long Duration TLP Time Domain 102
5.10 TLP-to-HBM Ratio 104
5.10.1 Comparison of Transmission Line Pulse (TLP) and Human Body Model (HBM) Pulse Width 104
5.11 Summary and Closing Comments 104
Problems 104
References 105
6 Very Fast Transmission Line Pulse (VF-TLP) Testing 108
6.1 History 108
6.2 Scope 108
6.3 Purpose 108
6.4 Pulse Waveform 109
6.4.1 Comparison of VF-TLP Versus TLP Waveform 110
6.5 Equivalent Circuit 111
6.6 Test Equipment Configuration 111
6.6.1 Current Source 112
6.6.2 Time Domain Reflection (TDR) 112
6.6.3 Time Domain Transmission (TDT) 112
6.6.4 Time Domain Reflection and Transmission (TDRT) 113
6.6.5 Early VF-TLP Systems 114
6.6.6 Commercial VF-TLP Test Systems 116
6.7 Test Sequence and Procedure 117
6.7.1 VF-TLP Pulse Analysis 118
6.7.2 Measurement Window 118
6.7.3 Measurement Analysis – VF-TLP Voltage Waveform 118
6.7.4 Measurement Analysis – Time Domain Reflectometry (TDR) Current Waveform 118
6.7.5 Measurement Analysis – Time Domain Transmission (TDR) Current–Voltage Characteristics 119
6.8 VF-TLP Pulsed I–V Characteristics 121
6.8.1 VF-TLP Pulsed I–V Characteristic Key Parameters 121
6.8.2 VF-TLP Power Versus Time Plot 122
6.8.3 VF-TLP Power Versus Time – Measurement Analysis 123
6.8.4 VF-TLP Power-to-Failure Versus Pulse Width Plot 123
6.8.5 VF-TLP and TLP Power-to-Failure Plot 124
6.9 Alternate Test Methods 124
6.9.1 Radio Frequency (RF) VF-TLP Systems 124
6.9.2 Ultrafast Transmission Line Pulse (UF-TLP) 125
6.10 Summary and Closing Comments 125
Problems 128
References 128
7 Iec 61000-4-2 130
7.1 History 130
7.2 Scope 130
7.3 Purpose 130
7.3.1 Air Discharge 131
7.3.2 Direct Contact Discharge 131
7.4 Pulse Waveform 131
7.4.1 Pulse Waveform Equation 132
7.5 Equivalent Circuit 133
7.6 Test Equipment 133
7.6.1 Test Configuration 134
7.6.2 ESD Guns 134
7.6.3 ESD Guns – Standard Versus Discharge Module 135
7.6.4 Human Body Model Versus IEC 61000-4-2 135
7.7 Test Sequence and Procedure 135
7.8 Failure Mechanisms 137
7.9 IEC 61000-4-2 ESD Current Paths 138
7.10 ESD Protection Circuitry Solutions 139
7.11 Alternative Test Methods 140
7.11.1 Automotive ESD Standards 141
7.11.2 Medical ESD Standards 142
7.11.3 Avionic ESD Standard 143
7.11.4 Military-Related ESD Standard 143
7.12 Summary and Closing Comments 143
Problems 143
References 144
8 Human Metal Model (HMM) 147
8.1 History 147
8.2 Scope 147
8.3 Purpose 148
8.4 Pulse Waveform 148
8.4.1 Pulse Waveform Equation 148
8.5 Equivalent Circuit 149
8.6 Test Equipment 149
8.7 Test Configuration 150
8.7.1 Horizontal Configuration 151
8.7.2 Vertical Configuration 151
8.7.3 HMM Fixture Board 152
8.8 Test Sequence and Procedure 153
8.8.1 Current Waveform Verification 154
8.8.2 Current Probe Verification Methodology 154
8.8.3 Current Probe Waveform Comparison 156
8.9 Failure Mechanisms 157
8.10 ESD Current Paths 158
8.11 ESD Protection Circuit Solutions 158
8.12 Summary and Closing Comments 160
Problems 160
References 161
9 Iec 61000-4-5 163
9.1 History 163
9.2 Scope 164
9.3 Purpose 164
9.4 Pulse Waveform 165
9.5 Equivalent Circuit 166
9.6 Test Equipment 166
9.7 Test Sequence and Procedure 168
9.8 Failure Mechanisms 168
9.9 IEC 61000-4-5 ESD Current Paths 170
9.10 ESD Protection Circuit Solutions 170
9.11 Alternate Test Methods 171
9.12 Summary and Closing Comments 171
Problems 172
References 172
10 Cable Discharge Event (CDE) 174
10.1 History 174
10.2 Scope 175
10.3 Purpose 175
10.4 Cable Discharge Event – Charging, Discharging, and Pulse Waveform 175
10.4.1 Charging Process 176
10.4.2 Discharging Process 176
10.4.3 Pulse Waveform 176
10.4.4 Comparison of CDE and IEC 61000-4-2 Pulse Waveform 176
10.5 Equivalent Circuit 178
10.6 Test Equipment 179
10.6.1 Commercial Test Systems 179
10.7 Test Measurement 180
10.7.1 Measurement 180
10.7.2 Measurement –Transmission Line Test Generators 180
10.7.3 Measurement – Low-Impedance Transmission Line Waveform 181
10.7.4 Schematic Capturing System Response to Reference Waveform 182
10.7.5 Tapered Transmission Lines 185
10.7.6 ESD Current Sensor 185
10.8 Test Procedure 185
10.9 Measurement of a Cable in Different Conditions 185
10.9.1 Test System Configuration and Diagram 187
10.9.2 Cable Configurations – Handheld Cable 189
10.9.3 Cable Configuration – Taped to Ground Plane 191
10.9.4 Cable Configurations – Pulse Analysis Summary 191
10.10 Transient Field Measurements 195
10.10.1 Transient Field Measurement of Short-Length Cable Discharge Events 195
10.10.2 Antenna-Induced Voltages 195
10.11 Telecommunication Cable Discharge Test System 195
10.12 Cable Discharge Current Paths 200
10.13 Failure Mechanisms 200
10.13.1 Cable Discharge Event Failure – Connector Failure 200
10.13.2 Cable Discharge Event Failure – Printed Circuit Board 201
10.13.3 Cable Discharge Event Failure – Semiconductor On-Chip 201
10.13.4 Cable Discharge Event (CDE)-Induced Latchup 201
10.14 Cable Discharge Event (CDE) Protection 201
10.14.1 RJ-45 Connectors 202
10.14.2 Printed Circuit Board Design Considerations 202
10.14.3 ESD Circuitry 202
10.14.4 Cable Discharge Event (CDE) ESD Protection Validation 203
10.15 Alternative Test Methods 203
10.16 Summary and Closing Comments 204
Problems 204
References 204
11 Latchup 206
11.1 History 206
11.2 Purpose 208
11.3 Scope 209
11.4 Pulse Waveform 209
11.5 Equivalent Circuit 209
11.6 Test Equipment 209
11.7 Test Sequence and Procedure 211
11.8 Failure Mechanisms 215
11.9 Latchup Current Paths 216
11.10 Latchup Protection Solutions 216
11.10.1 Latchup Protection Solutions – Semiconductor Process 219
11.10.2 Latchup Protection Solutions – Design Layout 219
11.10.3 Latchup Protection Solutions – Circuit Design 220
11.10.4 Latchup Protection Solutions – System Level Design 221
11.11 Alternate Test Methods 222
11.11.1 Photoemission Techniques – PICA–TLP 222
11.11.2 Photoemission Techniques – CCD Method 224
11.12 Single Event Latchup (SEL) Test Methods 224
11.13 Summary and Closing Comments 224
Problems 227
References 227
12 Electrical Overstress (EOS) 230
12.1 History 230
12.2 Scope 232
12.3 Purpose 233
12.4 Pulse Waveform 233
12.5 Equivalent Circuit 233
12.6 Test Equipment 234
12.7 Test Procedure and Sequence 234
12.8 Failure Mechanisms 236
12.8.1 Information Gathering 236
12.8.2 Failure Verification 237
12.8.3 Failure Site Identification and Localization 237
12.8.4 Root Cause Determination 238
12.8.5 Feedback of Root Cause 238
12.8.6 Corrective Actions 238
12.8.7 Documentation Reports 238
12.8.8 Statistical Analysis, Record Retention, and Control 238
12.9 Electrical Overstress (EOS) Protection Circuit Solutions 240
12.10 Electrical Overstress (EOS) Testing – TLP Method and EOS 249
12.10.1 Electrical Overstress (EOS) Testing – Long Duration Transmission Line Pulse (LD-TLP) Method 250
12.10.2 Electrical Overstress (EOS) Testing – Transmission Line Pulse (TLP) Method, EOS, and the Wunsch–Bell Model 250
12.10.3 Electrical Overstress (EOS) Testing – Limitations of the Transmission Line Pulse (TLP) Method for the Evaluation of EOS for Systems 250
12.10.4 Electrical Overstress (EOS) Testing – Electromagnetic Pulse (EMP) 251
12.11 Electrical Overstress (EOS) Testing – DC and Transient Latchup Testing 252
12.12 Summary and Closing Comments 252
Problems 252
References 253
13 Electromagnetic Compatibility (EMC) 257
13.1 History 257
13.2 Purpose 258
13.3 Scope 258
13.4 Pulse Waveform 258
13.5 Equivalent Circuit 259
13.6 Test Equipment 259
13.6.1 Commercial Test System 259
13.6.2 Scanning Systems 260
13.7 Test Procedures 261
13.7.1 ESD/EMC Scanning Test Procedure and Method 261
13.8 Failure Mechanisms 261
13.9 ESD/EMC Current Paths 263
13.10 EMC Solutions 264
13.11 Alternative Test Methods 266
13.11.1 Scanning Methodologies 266
13.11.2 Testing – Susceptibility and Vulnerability 266
13.11.3 EMC/ESD Scanning – Semiconductor Component and Populated Printed Circuit Board 267
13.12 EMC/ESD Product Evaluation – IC Prequalification 267
13.13 EMC/ESD Scanning Detection – Upset Evaluation 267
13.13.1 ESD/EMC Scanning Stimulus 267
13.14 EMC/ESD Product Qualification Process 268
13.14.1 EMC/ESD Reproducibility 268
13.14.2 EMC/ESD Failure Threshold Mapping and Histogram 268
13.14.3 ESD Immunity Test – IC Level 268
13.14.4 ESD Immunity Test – ATE Stage 271
13.15 Alternative ESD/EMC Scanning Methods 271
13.15.1 Alternative ESD/EMC Scanning Methods – Printed Circuit Board 271
13.15.2 Electromagnetic Interference (EMI) Emission Scanning Methodology 274
13.15.3 Radio Frequency (RF) Immunity Scanning Methodology 274
13.15.4 Resonance Scanning Methodology 275
13.15.5 Current Spreading Scanning Methodology 275
13.16 Current Reconstruction Methodology 276
13.16.1 EOS and Residual Current 276
13.16.2 Printed Circuit Board (PCB) Trace Electromagnetic Emissions 276
13.16.3 Test Procedure and Sequence 277
13.17 Printed Circuit Board (PCB) Design EMC Solutions 277
13.18 Summary and Closing Comments 280
Problems 281
References 282
A Glossary of Terms 284
B Standards 288
B. 1 ESD Association 288
B. 2 International Organization of Standards 289
B. 3 Iec 289
B. 4 Rtca 289
B. 5 Department of Defense 289
B. 6 Military Standards 289
B. 7 Airborne Standards and Lightning 290
Index 291
