Logic Design of NanoICS

1. Auflage 2004
ISBN: 978-0-8493-2766-7
Verlag: Taylor & Francis Inc

Buch, Englisch, 488 Seiten, Format (B × H): 156 mm x 235 mm, Gewicht: 817 g

Reihe: Nano- and Microscience, Engineering, Technology and Medicine

Today's engineers will confront the challenge of a new computing paradigm, relying on micro- and nanoscale devices. Logic Design of NanoICs builds a foundation for logic in nanodimensions and guides you in the design and analysis of nanoICs using CAD. The authors present data structures developed toward applications rather than a purely theoretical treatment.

Requiring only basic logic and circuits background, Logic Design of NanoICs draws connections between traditional approaches to design and modern design in nanodimensions. The book begins with an introduction to the directions and basic methodology of logic design at the nanoscale, then proceeds to nanotechnologies and CAD, graphical representation of switching functions and networks, word-level and linear word-level data structures, 3-D topologies based on hypercubes, multilevel circuit design, and fault-tolerant computation in hypercube-like structures. The authors propose design solutions and techniques, going beyond the underlying technology to provide more applied knowledge.

This design-oriented reference is written for engineers interested in developing the next generation of integrated circuitry, illustrating the discussion with approximately 250 figures and tables, 100 equations, 250 practical examples, and 100 problems. Each chapter concludes with a summary, references, and a suggested reading section.

Zielgruppe

Professional

Autoren/Hrsg.

Yanushkevich, Svetlana N.

Shmerko, Vlad P.

Lyshevski, Sergey Edward

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Preface. Acknowledgements. Introduction. Nanotechnologies. Basics of Logic Design in Nanospace. Word-level Data Structures. Nanospace and Hypercube-Like Data Structures. Nanodimensional Multilevel Circuits. Linear Word-level Models of Multilevel Circuits. Event-Driven Analysis of Hypercube-Like Topology. Nanodimensional Multivalued Circuits. Parallel Computation in Nanospace. Fault-Tolerant Computation. Information Measures in Nanodimensions. Index.

Über Autor(innen)

Svetlana N. Yanushkevich, Vlad P. Shmerko, Sergey Edward Lyshevski