Yoeli / Kol Verification of Systems and Circuits Using LOTOS, Petri Nets, and CCS

1. Auflage 2008
ISBN: 978-0-470-25339-7
Verlag: John Wiley & Sons
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 248 Seiten, E-Book

Reihe: Wiley Series on Parallel and Distributed Computing

A Step-by-Step Guide to Verification of Digital Systems
This practical book provides a step-by-step, interactiveintroduction to formal verification of systems and circuits. Thebook offers theoretical background and introduces the applicationof three powerful verification toolsets: LOTOS-based CADP, Petrinets-based PETRIFY, and CCS-based CWB. The book coversverification of modular asynchronous circuits, alternating-bitprotocols, arbiters, pipeline controllers, up-down counters, andphase converters, as well as many other verification examples.
Using the given detailed examples, exercises, and easy-to-followtutorials, complete with the downloadable toolsets available viareferenced Web sites, this book serves as an ideal text in advancedundergraduate and graduate courses in computer science andelectrical engineering. It is also valuable as a desktop referencefor practicing verification engineers who are interested inverifying that designed digital systems meet specifications andrequirements.

Autoren/Hrsg.

Yoeli, Michael

Kol, Rakefet

Inhaltsverzeichnis

1. Introduction.
1.1 Event-Based Approach.
1.2 Event-Based Systems.
1.3 Types of Verification.
1.4 Toolsets Used.
1.5 Level-Based Approach.
1.6 Overview of the Book.
1.7 References.
2. Processes.
2.1 Introduction.
2.2 Examples of Processes and Basic Concepts.
2.3 About Prefixing.
2.4 Process Graphs.
2.5 Choice Operator.
2.6 Another Process Example.
2.7 Equivalence.
2.8 Labeled Transition System (LTSs).
2.9 Parallel Operators.
2.10 Sequential Composition.
2.11 Further Reading.
2.12 Selected Solutions.
2.13 References.
3. From Digital hardware to Processes.
3.1 The C-Element.
3.2 The XOR-Gate.
3.3 TOGGLES.
3.4 Modulo-N Transaction counters.
3.5 Modular Networks.
3.6 Propositional Logic: A Review of Known Concepts.
3.7 Selected Solutions.
3.8 References.
4. Introducing LOTOS.
4.1 From Blot to Basic LOTOS.
4.2 Some semantics.
4.3 From LTS to LOTOS.
4.4 Comparing Parallel Operators.
4.5 Sequential Composition.
4.6 Hiding.
4.7 Equivalences and Preorders.
4.8 About CADP.
4.9 Full LOTOS--An Introduction.
4.10 The Regular Mu-calculus (RMC).
4.11 Further Reading.
4.12 Selected Solutions.
4.13 References.
5. Introducing Petri Nets.
5.1 About Petri Nets.
5.2 About Languages.
5.3 About PETRIFY.
5.4 Illustrating Petri Nets.
5.5 Labeled Nets.
5.6 Bounded Nets.
5.7 Observation Equivalence of LPNs.
5.8 From Blot to Petri Nets.
5.9 Liveness and Persistence.
5.10 Simple Reduction Rules.
5.11 Marked Graphs.
5.12 A Simple Net Algebra.
5.13 Arc-Weighted Nets.
5.14 Readers--Writers System.
5.15 Inhibitor Nets.
5.16 True Concurrency.
5.17 Further Reading.
5.18 Selected Solutions.
5.19 References.
6. Introducing CCS.
6.1 About CCS.
6.2 Operators 'Prefix' and 'Sum'.
6.3 Recursion.
6.4 Concurrency.
6.5 Equivalence.
6.6 Restriction.
6.7 CTL.
6.8 The Concurrency Workbench (CWB).
6.9 CCS and CWB Application Examples.
6.10 Further Reading.
6.11 Selected Solutions.
6.12 References.
7. Verification of Modular Asynchronous Circuits.
7.1 About Asynchronous Circuits.
7.2 XOR-Gates.
7.3 CEL-Circuit.
7.4 Other Modules.
7.5 Module Extensions.
7.6 Modular Networks.
7.7 Realizations.
7.8 Verification of Extended Modules.
7.9 Verification of Parallel Control Structures.
7.10 Further Reading.
7.11 Selected Solutions.
7.12 References.
8. Verification of Communication Protocols.
8.1 Introduction.
8.2 Two Simple Communication Protocols.
8.3 The Alternating Bit (AB) Protocol.
8.4 Further Reading.
8.5 Selected Solutions.
8.6 References.
9. Verification of Arbiters.
9.1 Introduction.
9.2 A random Arbiter (RGDA).
9.3 A Token-Ring Arbiter.
9.4 Further reading.
9.5 Selected Solutions.
9.6 References.
10. More Verification Case Studies.
10.1 Verification of Combinational Logic.
10.2 Verification of Asynchronous Pipeline Controllers.
10.3 Verification of Producer - Consumer Systems.
10.4 Verification Based on Design Approaches.
10.5 Verification of Toggles and Transition Counters.
10.6 Vending machines Verification--Revisited.
10.7 Pi-Realizations.
10.8 A Comparison of Equivalence Relations.
10.9 Selected Solutions.
10.10 References.
11. Guide to Further Studies.
11.1 Verification of Telecommunication Systems.
11.2 Verification Using Colored Petri Nets.
11.3 Verification of Traffic Signal Control Systems.
11.4 References.
Index.

Über Autor(innen)

Michael Yoeli, PhD, is Professor Emeritus in the Departmentof Computer Science, Technion, Israel. He is the author or editorof several books on digital networks and formal verification. Hisresearch interests include theory and applications of Petri nets,formal verification of hardware design, formal verification andsynthesis of modular asynchronous networks, and computer-assistedanalysis of parallel systems. He was awarded a Certificate ofAcknowledgment by the Israel Section of the IEEE and the IsraelChapter of the IEEE Computer Society.
Rakefet Kol, PhD, is a member of the ElectricalEngineering Department, Technion, Israel. Her research interestsinclude computer architectures, asynchronous design, formalverification of hardware designs, and software engineering. She isa senior member of the IEEE and a professional member of theACM.