Harris Digital Design and Computer Architecture

1. Auflage 2010
ISBN: 978-0-08-054706-0
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 592 Seiten

Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of Digital Design and Computer Architecture, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works--even if they have no formal background in design or architecture beyond an introductory class. David Harris and Sarah Harris combine an engaging and humorous writing style with an updated and hands-on approach to digital design.
· Unique presentation of digital logic design from the perspective of computer architecture using a real instruction set, MIPS.
· Side-by-side examples of the two most prominent Hardware Design Languages--VHDL and Verilog--illustrate and compare the ways the each can be used in the design of digital systems.
· Worked examples conclude each section to enhance the reader's understanding and retention of the material.
· Companion Web site includes links to CAD tools for FPGA design from Xilinx, lecture slides, laboratory projects, and solutions to exercises.

David Money Harris is an associate professor of engineering at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Evans & Sutherland, and other design companies.
David's passions include teaching, building chips, and exploring the outdoors. When he is not at work, he can usually be found hiking, mountaineering, or rock climbing. He particularly enjoys hiking with his son, Abraham, who was born at the start of this book project. David holds about a dozen patents and is the author of three other textbooks on chip design, as well as two guidebooks to the Southern California mountains.

Autoren/Hrsg.

Harris, David

Harris, Sarah

Inhaltsverzeichnis

1;Front cover;1
2;In Praise of Digital Design and Computer Architecture;2
3;About the Authors;5
4;Title page;6
5;Copyright page;7
6;Table of contents;10
7;Preface;18
7.1;FEATURES;19
7.2;ONLINE SUPPLEMENTS;20
7.3;HOW TO USE THE SOFTWARE TOOLS IN A COURSE;20
7.3.1;Xilinx ISE WebPACK;20
7.3.2;Synplify Pro;21
7.3.3;PCSPIM;21
7.4;LABS;21
7.5;BUGS;22
7.6;ACKNOWLEDGMENTS;22
8;Chapter 1 From Zero to One;26
8.1;1.1 THE GAME PLAN;26
8.2;1.2 THE ART OF MANAGING COMPLEXITY;27
8.2.1;1.2.1 Abstraction;27
8.2.2;1.2.2 Discipline;28
8.2.3;1.2.3 The Three -Y’s;29
8.3;1.3 THE DIGITAL ABSTRACTION;30
8.4;1.4 NUMBER SYSTEMS;32
8.4.1;1.4.1 Decimal Numbers;32
8.4.2;1.4.2 Binary Numbers;32
8.4.3;1.4.3 Hexadecimal Numbers;34
8.4.4;1.4.4 Bytes, Nibbles, and All That Jazz;36
8.4.5;1.4.5 Binary Addition;37
8.4.6;1.4.6 Signed Binary Numbers;38
8.5;1.5 LOGIC GATES;42
8.5.1;1.5.1 NOT Gate;43
8.5.2;1.5.2 Buffer;43
8.5.3;1.5.3 AND Gate;43
8.5.4;1.5.4 OR Gate;44
8.5.5;1.5.5 Other Two-Input Gates;44
8.5.6;1.5.6 Multiple-Input Gates;44
8.6;1.6 BENEATH THE DIGITAL ABSTRACTION;45
8.6.1;1.6.1 Supply Voltage;45
8.6.2;1.6.2 Logic Levels;45
8.6.3;1.6.3 Noise Margins;46
8.6.4;1.6.4 DC Transfer Characteristics;46
8.6.5;1.6.5 The Static Discipline;47
8.7;1.7 CMOS TRANSISTORS;49
8.7.1;1.7.1 Semiconductors;50
8.7.2;1.7.2 Diodes;50
8.7.3;1.7.3 Capacitors;51
8.7.4;1.7.4 nMOS and pMOS Transistors;51
8.7.5;1.7.5 CMOS NOT Gate;54
8.7.6;1.7.6 Other CMOS Logic Gates;54
8.7.7;1.7.7 Transmission Gates;56
8.7.8;1.7.8 Pseudo-nMOS Logic;56
8.8;1.8 POWER CONSUMPTION;57
8.9;1.9 SUMMARY AND A LOOK AHEAD;58
8.10;Exercises;60
8.11;Interview Questions;71
9;Chapter 2 Combinational Logic Design;74
9.1;2.1 INTRODUCTION;74
9.2;2.2 BOOLEAN EQUATIONS;77
9.2.1;2.2.1 Terminology;77
9.2.2;2.2.2 Sum-of-Products Form;77
9.2.3;2.2.3 Product-of-Sums Form;79
9.3;2.3 BOOLEAN ALGEBRA;79
9.3.1;2.3.1 Axioms;80
9.3.2;2.3.2 Theorems of One Variable;80
9.3.3;2.3.3 Theorems of Several Variables;81
9.3.4;2.3.4 The Truth Behind It All;83
9.3.5;2.3.5 Simplifying Equations;84
9.4;2.4 FROM LOGIC TO GATES;85
9.5;2.5 MULTILEVEL COMBINATIONAL LOGIC;88
9.5.1;2.5.1 Hardware Reduction;89
9.5.2;2.5.2 Bubble Pushing;90
9.6;2.6 X’S AND Z’S, OH MY;92
9.6.1;2.6.1 Illegal Value: X;92
9.6.2;2.6.2 Floating Value: Z;93
9.7;2.7 KARNAUGH MAPS;94
9.7.1;2.7.1 Circular Thinking;95
9.7.2;2.7.2 Logic Minimization with K-Maps;96
9.7.3;2.7.3 Don’t Cares;100
9.7.4;2.7.4 The Big Picture;101
9.8;2.8 COMBINATIONAL BUILDING BLOCKS;102
9.8.1;2.8.1 Multiplexers;102
9.8.2;2.8.2 Decoders;105
9.9;2.9 TIMING;107
9.9.1;2.9.1 Propagation and Contamination Delay;107
9.9.2;2.9.2 Glitches;111
9.10;2.10 SUMMARY;114
9.11;Exercises;116
9.12;Interview Questions;123
10;Chapter 3 Sequential Logic Design;126
10.1;3.1 INTRODUCTION;126
10.2;3.2 LATCHES AND FLIP-FLOPS;126
10.2.1;3.2.1 SR Latch;128
10.2.2;3.2.2 D Latch;130
10.2.3;3.2.3 D Flip-Flop;131
10.2.4;3.2.4 Register;131
10.2.5;3.2.5 Enabled Flip-Flop;132
10.2.6;3.2.6 Resettable Flip-Flop;133
10.2.7;3.2.7 Transistor-Level Latch and Flip-Flop Designs;133
10.2.8;3.2.8 Putting It All Together;135
10.3;3.3 SYNCHRONOUS LOGIC DESIGN;136
10.3.1;3.3.1 Some Problematic Circuits;136
10.3.2;3.3.2 Synchronous Sequential Circuits;137
10.3.3;3.3.3 Synchronous and Asynchronous Circuits;139
10.4;3.4 FINITE STATE MACHINES;140
10.4.1;3.4.1 FSM Design Example;140
10.4.2;3.4.2 State Encodings;146
10.4.3;3.4.3 Moore and Mealy Machines;149
10.4.4;3.4.4 Factoring State Machines;152
10.4.5;3.4.5 FSM Review;155
10.5;3.5 TIMING OF SEQUENTIAL LOGIC;156
10.5.1;3.5.1 The Dynamic Discipline;157
10.5.2;3.5.2 System Timing;158
10.5.3;3.5.3 Clock Skew;163
10.5.4;3.5.4 Metastability;166
10.5.5;3.5.5 Synchronizers;167
10.5.6;3.5.6 Derivation of Resolution Time;169
10.6;3.6 PARALLELISM;172
10.7;3.7 SUMMARY;176
10.8;Exercises;178
10.9;Untitled;188
11;Chapter 4 Hardware Description Languages;190
11.1;4.1 INTRODUCTION;190
11.1.1;4.1.1 Modules;190
11.1.2;4.1.2 Language Origins;191
11.1.3;4.1.3 Simulation and Synthesis;192
11.2;4.2 COMBINATIONAL LOGIC;194
11.2.1;4.2.1 Bitwise Operators;194
11.2.2;4.2.3 Reduction Operators;197
11.2.3;4.2.2 Comments and White Space;197
11.2.4;4.2.4 Conditional Assignment;198
11.2.5;4.2.5 Internal Variables;199
11.2.6;4.2.6 Precedence;201
11.2.7;4.2.7 Numbers;202
11.2.8;4.2.8 Z’s and X’s;202
11.2.9;4.2.9 Bit Swizzling;205
11.2.10;4.2.10 Delays;205
11.2.11;4.2.11 VHDL Libraries and Types;206
11.3;4.3 STRUCTURAL MODELING;208
11.4;4.4 SEQUENTIAL LOGIC;213
11.4.1;4.4.1 Registers;213
11.4.2;4.4.2 Resettable Registers;214
11.4.3;4.4.3 Enabled Registers;216
11.4.4;4.4.4 Multiple Registers;217
11.4.5;4.4.5 Latches;218
11.5;4.5 MORE COMBINATIONAL LOGIC;218
11.5.1;4.5.1 Case Statements;221
11.5.2;4.5.2 If Statements;222
11.5.3;4.5.3 Verilog casez;224
11.5.4;4.5.4 Blocking and Nonblocking Assignments;224
11.6;4.6 FINITE STATE MACHINES;229
11.7;4.7 PARAMETERIZED MODULES;234
11.8;4.8 TESTBENCHES;237
11.9;4.9 SUMMARY;241
11.10;Exercises;242
11.10.1;Verilog Exercises;247
11.10.2;VHDL Exercises;250
11.11;Interview Questions;253
12;Chapter 5 Digital Building Blocks;256
12.1;5.1 INTRODUCTION;256
12.2;5.2 ARITHMETIC CIRCUITS;256
12.2.1;5.2.1 Addition;256
12.2.2;5.2.2 Subtraction;263
12.2.3;5.2.3 Comparators;263
12.2.4;5.2.4 ALU;265
12.2.5;5.2.5 Shifters and Rotators;267
12.2.6;5.2.6 Multiplication;269
12.2.7;5.2.7 Division;270
12.2.8;5.2.8 Further Reading;271
12.3;5.3 NUMBER SYSTEMS;272
12.3.1;5.3.1 Fixed-Point Number Systems;272
12.3.2;5.3.2 Floating-Point Number Systems;273
12.4;5.4 SEQUENTIAL BUILDING BLOCKS;277
12.4.1;5.4.1 Counters;277
12.4.2;5.4.2 Shift Registers;278
12.5;5.5 MEMORY ARRAYS;280
12.5.1;5.5.1 Overview;280
12.5.2;5.5.2 Dynamic Random Access Memory;283
12.5.3;5.5.3 Static Random Access Memory (SRAM);283
12.5.4;5.5.4 Area and Delay;284
12.5.5;5.5.5 Register Files;284
12.5.6;5.5.6 Read Only Memory;285
12.5.7;5.5.7 Logic Using Memory Arrays;287
12.5.8;5.5.8 Memory HDL;287
12.6;5.6 LOGIC ARRAYS;289
12.6.1;5.6.1 Programmable Logic Array;289
12.6.2;5.6.2 Field Programmable Gate Array;291
12.6.3;5.6.3 Array Implementations;296
12.7;5.7 SUMMARY;297
12.8;Exercises;299
12.9;Interview Questions;309
13;Chapter 6 Architecture;312
13.1;6.1 INTRODUCTION;312
13.2;6.2 ASSEMBLY LANGUAGE;313
13.2.1;6.2.1 Instructions;313
13.2.2;6.2.2 Operands: Registers, Memory, and Constants;315
13.3;6.3 MACHINE LANGUAGE;322
13.3.1;6.3.1 R-type Instructions;322
13.3.2;6.3.2 I-Type Instructions;324
13.3.3;6.3.3 J-type Instructions;325
13.3.4;6.3.4 Interpreting Machine Language Code;325
13.3.5;6.3.5 The Power of the Stored Program;326
13.4;6.4 PROGRAMMING;327
13.4.1;6.4.1 Arithmetic/Logical Instructions;327
13.4.2;6.4.2 Branching;331
13.4.3;6.4.3 Conditional Statements;333
13.4.4;6.4.4 Getting Loopy;334
13.4.5;6.4.5 Arrays;337
13.4.6;6.4.6 Procedure Calls;342
13.5;6.5 ADDRESSING MODES;350
13.6;6.6 LIGHTS, CAMERA, ACTION: COMPILING, ASSEMBLING, AND LOADING;353
13.6.1;6.6.1 The Memory Map;353
13.6.2;6.6.2 Translating and Starting a Program;354
13.7;6.7 ODDS AND ENDS;359
13.7.1;6.7.1 Pseudoinstructions;359
13.7.2;6.7.2 Exceptions;360
13.7.3;6.7.3 Signed and Unsigned Instructions;361
13.7.4;6.7.4 Floating-Point Instructions;363
13.8;6.8 REAL-WORLD PERSPECTIVE: IA-32 ARCHITECTURE;364
13.8.1;6.8.1 IA-32 Registers;365
13.8.2;6.8.2 IA-32 Operands;365
13.8.3;6.8.3 Status Flags;367
13.8.4;6.8.4 IA-32 Instructions;367
13.8.5;6.8.5 IA-32 Instruction Encoding;369
13.8.6;6.8.6 Other IA-32 Peculiarities;371
13.8.7;6.8.7 The Big Picture;372
13.9;6.9 SUMMARY;372
13.10;Exercises;374
13.11;Interview Questions;384
14;Chapter 7 Microarchitecture;386
14.1;7.1 INTRODUCTION;386
14.1.1;7.1.1 Architectural State and Instruction Set;386
14.1.2;7.1.2 Design Process;387
14.1.3;7.1.3 MIPS Microarchitectures;389
14.2;7.2 PERFORMANCE ANALYSIS;389
14.3;7.3 SINGLE-CYCLE PROCESSOR;391
14.3.1;7.3.1 Single-Cycle Datapath;391
14.3.2;7.3.2 Single-Cycle Control;397
14.3.3;7.3.3 More Instructions;400
14.3.4;7.3.4 Performance Analysis;403
14.4;7.4 MULTICYCLE PROCESSOR;404
14.4.1;7.4.1 Multicycle Datapath;405
14.4.2;7.4.2 Multicycle Control;411
14.4.3;7.4.3 More Instructions;418
14.4.4;7.4.4 Performance Analysis;420
14.5;7.5 PIPELINED PROCESSOR;424
14.5.1;7.5.1 Pipelined Datapath;427
14.5.2;7.5.2 Pipelined Control;428
14.5.3;7.5.3 Hazards;429
14.5.4;7.5.4 More Instructions;441
14.5.5;7.5.5 Performance Analysis;441
14.6;7.6 HDL REPRESENTATION;444
14.6.1;7.6.1 Single-Cycle Processor;445
14.6.2;7.6.2 Generic Building Blocks;449
14.6.3;7.6.3 Testbench;451
14.7;7.7 EXCEPTIONS;454
14.8;7.8 ADVANCED MICROARCHITECTURE;458
14.8.1;7.8.1 Deep Pipelines;458
14.8.2;7.8.2 Branch Prediction;460
14.8.3;7.8.3 Superscalar Processor;461
14.8.4;7.8.4 Out-of-Order Processor;464
14.8.5;7.8.5 Register Renaming;466
14.8.6;7.8.6 Single Instruction Multiple Data;468
14.8.7;7.8.7 Multithreading;469
14.8.8;7.8.8 Multiprocessors;470
14.9;7.9 REAL-WORLD PERSPECTIVE: IA-32 MICROARCHITECTURE;470
14.10;7.10 SUMMARY;476
14.11;Exercises;478
14.12;Untitled;484
15;Chapter 8 Memory Systems;486
15.1;8.1 INTRODUCTION;486
15.2;8.2 MEMORY SYSTEM PERFORMANCE ANALYSIS;490
15.3;8.3 CACHES;491
15.3.1;8.3.1 What Data Is Held in the Cache?;492
15.3.2;8.3.2 How Is the Data Found?;493
15.3.3;8.3.3 What Data Is Replaced?;501
15.3.4;8.3.4 Advanced Cache Design;502
15.3.5;8.3.5 The Evolution of MIPS Caches;506
15.4;8.4 VIRTUAL MEMORY;507
15.4.1;8.4.1 Address Translation;509
15.4.2;8.4.2 The Page Table;511
15.4.3;8.4.3 The Translation Lookaside Buffer;513
15.4.4;8.4.4 Memory Protection;514
15.4.5;8.4.5 Replacement Policies;515
15.4.6;8.4.6 Multilevel Page Tables;515
15.5;8.5 MEMORY-MAPPED I/O;517
15.6;8.6 REAL-WORLD PERSPECTIVE: IA-32 MEMORY AND I/O SYSTEMS;522
15.6.1;8.6.1 IA-32 Cache Systems;522
15.6.2;8.6.2 IA-32 Virtual Memory;524
15.6.3;8.6.3 IA-32 Programmed I/O;525
15.7;8.7 SUMMARY;525
15.8;EPILOGUE;526
15.9;Exercises;527
15.10;Interview Questions;535
16;Appendix A Digital System Implementation;538
16.1;A .1 INTRODUCTION;538
16.2;A.2 74XX LOGIC;538
16.2.1;A.2.1 Logic Gates;539
16.2.2;A.2.2 Other Functions;539
16.3;A.3 PROGRAMMABLE LOGIC;539
16.3.1;A.3.1 PROMs;539
16.3.2;A.3.2 PLAs;543
16.3.3;A.3.3 FPGAs;544
16.4;A.4 APPLICATION-SPECIFIC INTEGRATED CIRCUITS;546
16.5;A.5 DATA SHEETS;546
16.6;A.6 LOGIC FAMILIES;552
16.7;A.7 PACKAGING AND ASSEMBLY;554
16.8;A.8 TRANSMISSION LINES;557
16.8.1;A.8.1 Matched Termination;559
16.8.2;A.8.2 Open Termination;561
16.8.3;A.8.3 Short Termination;562
16.8.4;A.8.4 Mismatched Termination;562
16.8.5;A.8.5 When to Use Transmission Line Models;565
16.8.6;A.8.6 Proper Transmission Line Terminations;565
16.8.7;A.8.7 Derivation of Z0;567
16.8.8;A.8.8 Derivation of the Reflection Coefficient;568
16.8.9;A.8.9 Putting It All Together;569
16.9;A.9 ECONOMICS;570
17;Appendix B MIPS Instructions;574
18;Further Reading;578
19;Index;580