Timing Optimization Through Clock Skew Scheduling

Softcover Nachdruck of the original 1. Auflage 2000
ISBN: 978-1-4613-6985-1
Verlag: Springer US

Buch, Englisch, 194 Seiten, Paperback, Format (B × H): 155 mm x 235 mm, Gewicht: 341 g

History of the Book The last three decades have witnessed an explosive development in integrated circuit fabrication technologies. The complexities of cur­ rent CMOS circuits are reaching beyond the 100 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the successful design and implemen­ tation of thousands of high performance, large scale integrated circuits. This research monograph originated from a body of doctoral disserta­ tion research completed by the first author at the University of Rochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution net­ work in large scale, high performance digital synchronous circuits and particularly, on algorithms for non-zero clock skew scheduling. During the development of this research, it has become clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical de­ velopments in this area have been slow to reach the designers' desktops.

Zielgruppe

Research

Autoren/Hrsg.

Kourtev, Ivan S.

Taskin, Baris

Friedman, Eby G.

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Energietechnik | Elektrotechnik Elektrotechnik

Inhaltsverzeichnis

1. Introduction.- 2. VLSI Systems.- 2.1 Signal Representation.- 2.2 Synchronous VLSI Systems.- 2.3 The VLSI Design Process.- 2.4 Summary.- 3. Signal Delay In Vlsi Systems.- 3.1 Delay Metrics.- 3.2 Devices and Interconnections.- 4. Timing Properties Of Synchronous Systems.- 4.1 Storage Elements.- 4.2 Latches.- 4.3 Parameters of Latches.- 4.4 Flip-Flops.- 4.5 Parameters of Flip-Flops.- 4.6 The Clock Signal.- 4.7 Single-Phase Path with Flip-Flops.- 4.8 Single-Phase Path with Latches.- 4.9 A Final Note.- 5. Clock Scheduling and Clock Tree Synthesis.- 5.1 Background.- 5.2 Definitions and Graphical Model.- 5.3 Clock Scheduling.- 5.4 Structure of the Clock Distribution Network.- 5.5 Solution of the Clock Tree Synthesis Problem.- 5.6 Software Implementation.- 6. Clock Scheduling For Improved Reliability.- 6.1 Problem Formulation.- 6.2 Derivation of the QP Algorithm.- 7. Practical Considerations.- 7.1 Computational Analysis.- 7.2 Unconstrained Basis Skews.- 7.3 I/O Registers and Target Delays.- 8. Experimental Results.- 8.1 Description of Computer Implementation.- 8.2 Graphical Illustrations of Results.- 9. Conclusions.- 10. Future Directions.- 10.1 Algorithmic Enhancements.- 10.2 Practical Considerations.- References.- Appendices.- A- Numerical Illustration of Algorithms.- A.1 Algorithm LMCS-1.- A.2 Algorithm LMCS-2.- A.3 Algorithm CSD.- B- Glossary of Terms.- C- Graphical Illustration of Results.- About the Authors.