A Pipelined Multi-Core Machine with Operating System Support

Hardware Implementation and Correctness Proof
1. Auflage 2020
ISBN: 978-3-030-43242-3
Verlag: Springer International Publishing

Buch, Englisch, Band 9999, 628 Seiten, Paperback, Format (B × H): 155 mm x 235 mm, Gewicht: 961 g

Reihe: Theoretical Computer Science and General Issues

This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

• MIPS instruction set architecture (ISA) for application and for system programming

• cache coherent memory system

• store buffers in front of the data caches

• interrupts and exceptions

• memory management units (MMUs)

• pipelined processors: the classical five-stage pipeline is extended by two pipeline

stages for address translation

• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

• I/O-interrupt controller and a disk

Zielgruppe

Research

Autoren/Hrsg.

Lutsyk, Petro

Paul, Wolfgang J.

Oberhauser, Jonas

Fachgebiete

• Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Programmierung: Methoden und Allgemeines
• Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Programmier- und Skriptsprachen

Inhaltsverzeichnis

Introductory material.- on hierarchical hardware design.- hardware library.- basic processor design.- pipelining.- cache memory systems.- interrupt mechanism.- self modification, instruction buffer and nondeterministic ISA.- memory management units.- store buffers.- multi-core processors.- advanced programmable interrupt controllers (APICs).- adding a disk.- I/O apic.